Quantum arithmetic operations play a vital role in modern quantum computing applications such as cryptography, signal processing, and large-scale scientific computation. However, conventional quantum multiplication architectures often suffer from high computational complexity, increased Toffoli depth, and excessive T gate consumption, which limit their practical implementation on scalable quantum hardware. This paper presents an optimized distributed quantum multiplication framework based on the Residue Number System (RNS) to improve computational efficiency and scalability. The proposed approach divides large multiplication tasks into multiple modular arithmetic operations that are executed independently across distributed quantum processing units. A Quantum Diminished-1 Modulo (2ⁿ+1) multiplier is incorporated as the fundamental computational block to achieve faster modular multiplication with reduced gate complexity. Performance analysis is carried out for quantum outputs ranging from 6 to 16 qubits and compared with traditional quantum multiplication methods. Experimental results demonstrate significant improvements in resource optimization, including reduced Toffoli depth, minimized T gate utilization, and enhanced execution speed. The proposed framework provides a scalable and efficient solution for next-generation distributed quantum arithmetic systems and supports the development of practical large-scale quantum computing architectures.
Quantum arithmetic operations play a vital role in modern quantum computing applications such as cryptography, signal processing, and large-scale scientific computation. However, conventional quantum multiplication architectures often suffer from high computational complexity, increased Toffoli depth, and excessive T gate consumption, which limit their practical implementation on scalable quantum hardware. This paper presents an optimized distributed quantum multiplication framework based on the Residue Number System (RNS) to improve computational efficiency and scalability. The proposed approach divides large multiplication tasks into multiple modular arithmetic operations that are executed independently across distributed quantum processing units. A Quantum Diminished-1 Modulo (2ⁿ+1) multiplier is incorporated as the fundamental computational block to achieve faster modular multiplication with reduced gate complexity. Performance analysis is carried out for quantum outputs ranging from 6 to 16 qubits and compared with traditional quantum multiplication methods. Experimental results demonstrate significant improvements in resource optimization, including reduced Toffoli depth, minimized T gate utilization, and enhanced execution speed. The proposed framework provides a scalable and efficient solution for next-generation distributed quantum arithmetic systems and supports the development of practical large-scale quantum computing architectures.
A key component of quantum algorithms is the efficient multiplication of quantum states; nevertheless, the scalability of traditional quantum multipliers on quantum hardware is frequently limited by high Toffoli depth and excessive T gate utilization. This research introduces a distributed quantum multiplication framework based on the Residue Number System (RNS) that performs numerous quantum modulo multiplication operations across different quantum processors or computational tasks. We present a Quantum Diminished-1 Modulo (2⋅+1) Multiplier inside this framework, which is a crucial element that improves the effectiveness of RNS-based distributed multiplication. For outputs between 6 and 16 qubits, we present a thorough examination of the quantum resource requirements and contrast the suggested method with a traditional non-distributed quantum multiplier. The results underscore the promise of the suggested strategy for scalable and resource-efficient quantum arithmetic, showing reductions of up to 46.02% in Toffoli depth and 34.48% to 86.25% in T gate count.
Multiplication of quantum states is a frequently used function or subroutine in quantum algorithms and applications, making quantum multipliers an essential component of quantum arithmetic. However, quantum multiplier circuits suffer from high Toffoli depth and T gate usage, which ultimately affects their scalability and applicability on quantum computers. To address these issues, we propose utilizing the Residue Number System (RNS) based distributed quantum multiplication, which executes multiple quantum modulo multiplication circuits across quantum computers or jobs with lower Toffoli depth and T gate usage. Towards this end, we propose a design of Quantum Diminished-1 Modulo(2n+1)Multiplier, an essential component of RNS based distributed quantum multiplication. We provide estimates of quantum resource usage and compare them with those of an existing non-distributed quantum multiplier for 6 to 16 qubit sized output. Our comparative analysis estimates up to 46.018% lower Toffoli depth, and reduction in T gates of 34.483% to 86.25%.
Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2k, 2p-1}. Modulo 2n-1, 2n, and 2n+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2n-1, 2n+k, 2n+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.
Quantum Arithmetic faces limitations such as noise and resource constraints in the current Noisy Intermediate Scale Quantum (NISQ) era quantum computers. We propose using Distributed Quantum Computing (DQC) to overcome these limitations by substituting a higher depth quantum addition circuit with Residue Number System (RNS) based quantum modulo adders. The RNS-based distributed quantum addition circuits possess lower depth and are distributed across multiple quantum computers/jobs, resulting in higher noise resilience. We propose the Quantum Superior Modulo Addition based on RNS Tool (QSMART), which can generate RNS sets of quantum adders based on multiple factors such as depth, range, and efficiency. We also propose a novel design of Quantum Diminished-1 Modulo (2n+ 1) Adder (QDMA), which forms a crucial part of RNS-based distributed quantum addition and the QSMART tool. We demonstrate the higher noise resilience of the Residue Number System (RNS) based distributed quantum addition by conducting simulations modeling Quantinuum's HI ion trap-based quantum computer. Our simulations demonstrate that RNS-based distributed quantum addition has 11.36% to 133.15% higher output probability over 6-bit to 10-bit non-distributed quantum full adders, indicating higher noise fidelity. Furthermore, we present a scalable way of achieving distributed quantum addition higher than limited otherwise by the 20-qubit range of Quantinuum HI.
In recent decades, quantum computing has witnessed remarkable progress, achieved through various advancements across the technology stack, such as quantum error-correcting codes and quantum algorithms. It is noteworthy that several promising algorithms incorporate quantum arithmetic circuits as fundamental building blocks. However, the inherent properties of quantum circuits challenge the efficiency of quantum arithmetic circuits, prompting creative solutions. While several quantum arithmetic circuits have been proposed, there is still a substantial gap in quantum arithmetic circuits optimization. For example, methods for integrating classical techniques such as high radix strategy into quantum designs still remain underexplored, highlighting a significant space for further advancement. This thesis aims to improve the performance of quantum arithmetic designs by integrating classical arithmetic circuit design techniques. Specifically, this thesis contains the following research: (1) The utilization of classical higher radix strategy to enhance quantum addition, reducing overall cost by lowering T-depth and T-count. The proposed design outperforms existing quantum carry-lookahead adders. (2) The application of Ling structure, achieving a reduced Toffoli-depth of 4log(n/2). (3) The exploration of the Kogge-Stone architecture, resulting in the lowest Toffoli-depth of log(n) for quantum adders. (4) The development of an efficient modular addition framework using carry-save architecture, demonstrating a 33.3% improvement in Toffoli depth compared to existing designs. (5) The design of an optimized quantum non-restoring divider framework. (6) A comprehensive overview of current advancements in quantum arithmetic designs, offering insights into potential research directions. These proposed designs are mapped to real-world quantum hardware architectures, including Noisy Intermediate-Scale Quantum systems, to validate their functionality and evaluate efficiency. Their applications in quantum machine learning and cryptography further underscore the broader impact of these improvements. Overall, this thesis makes significant advancements in reducing quantum circuit depth and improving resource efficiency, contributing to the development of scalable and efficient large-scale quantum circuits. By adapting classical design strategies to quantum circuits, it not only enhances various quantum circuit designs but also fosters further exploration at the intersection of classical and quantum computing.
The Quantum Leading-Zero/One Counter (QLZOC) is a fundamental component in quantum arithmetic, playing a critical role in normalization, floating-point units, dynamic range scaling, and logarithmic approximations. Conventional designs primarily rely on direct Boolean-to-quantum mapping, which results in inefficient resource utilization such as irregular gate growth and width-dependent resource overhead. In this work, we propose a scalable, modular, and resource efficient architecture for QLZOC by reformulating the counting process into a sequence of systematic conditional bit-flip operations. Moreover, our design achieves functional polymorphism so that the same design can be easily toggled between zero and one detection, while ensuring seamless scalability to any bit-width without manual re-tuning. We further introduce a Parallel QLZOC (PQLZOC) variant and a Fan-Out optimized (FO-PQLZOC) design. In this work, we evaluate resource efficiency based on the classic criteria about T gates, including the number of total T gates being used (T-count) and the number of sequential T gate layers (T-depth). By exploiting the properties of all-zero/one qubit blocks and a hierarchical merge strategy, the proposed FO-PQLZOC reduces the T-depth from O(m) to O(log m), where m is the input size. Comparative analysis demonstrates that our optimized architecture achieves a 40% reduction in T-count and a 60% reduction in T-depth over state-of-the-art designs, providing a high-performance, T-gate efficient solution for general-purpose quantum arithmetic processors.