The Quantum Leading-Zero/One Counter (QLZOC) is a fundamental component in quantum arithmetic, playing a critical role in normalization, floating-point units, dynamic range scaling, and logarithmic approximations. Conventional designs primarily rely on direct Boolean-to-quantum mapping, which results in inefficient resource utilization such as irregular gate growth and width-dependent resource overhead. In this work, we propose a scalable, modular, and resource efficient architecture for QLZOC by reformulating the counting process into a sequence of systematic conditional bit-flip operations. Moreover, our design achieves functional polymorphism so that the same design can be easily toggled between zero and one detection, while ensuring seamless scalability to any bit-width without manual re-tuning. We further introduce a Parallel QLZOC (PQLZOC) variant and a Fan-Out optimized (FO-PQLZOC) design. In this work, we evaluate resource efficiency based on the classic criteria about T gates, including the number of total T gates being used (T-count) and the number of sequential T gate layers (T-depth). By exploiting the properties of all-zero/one qubit blocks and a hierarchical merge strategy, the proposed FO-PQLZOC reduces the T-depth from O(m) to O(log m), where m is the input size. Comparative analysis demonstrates that our optimized architecture achieves a 40% reduction in T-count and a 60% reduction in T-depth over state-of-the-art designs, providing a high-performance, T-gate efficient solution for general-purpose quantum arithmetic processors.
The Quantum Leading-Zero/One Counter (QLZOC) is a fundamental component in quantum arithmetic, playing a critical role in normalization, floating-point units, dynamic range scaling, and logarithmic approximations. Conventional designs primarily rely on direct Boolean-to-quantum mapping, which results in inefficient resource utilization such as irregular gate growth and width-dependent resource overhead. In this work, we propose a scalable, modular, and resource efficient architecture for QLZOC by reformulating the counting process into a sequence of systematic conditional bit-flip operations. Moreover, our design achieves functional polymorphism so that the same design can be easily toggled between zero and one detection, while ensuring seamless scalability to any bit-width without manual re-tuning. We further introduce a Parallel QLZOC (PQLZOC) variant and a Fan-Out optimized (FO-PQLZOC) design. In this work, we evaluate resource efficiency based on the classic criteria about T gates, including the number of total T gates being used (T-count) and the number of sequential T gate layers (T-depth). By exploiting the properties of all-zero/one qubit blocks and a hierarchical merge strategy, the proposed FO-PQLZOC reduces the T-depth from O(m) to O(log m), where m is the input size. Comparative analysis demonstrates that our optimized architecture achieves a 40% reduction in T-count and a 60% reduction in T-depth over state-of-the-art designs, providing a high-performance, T-gate efficient solution for general-purpose quantum arithmetic processors.
Reversible logic is essential in quantum computing due to its ability to preserve information and establish a one-to-one mapping between inputs and outputs. The Clifford+T gate set, known for supporting fault-tolerant quantum circuits, offers resilience against decoherence but introduces high implementation costs, particularly due to the T gate's resource intensity. In this work, we propose a new and efficient quantum multiplexer design, the Quantum Clifford T-MUX, designed entirely within the Clifford+T framework. This multiplexer minimizes T-count and avoids the use of ancillary qubits, both critical factors for practical, fault-tolerant quantum computing. As part of this architecture, we present a newly designed fault-tolerant Peres gate using only Clifford+T gates, which serves as a fundamental building block in the T-MUX construction. The proposed T-MUX achieves reduced T-count, no garbage output, and improved efficiency compared to traditional designs. These improvements position it as a valuable component for building scalable quantum Arithmetic Logic Units (ALUs), data buses, and memory systems. Overall, this work contributes toward the development of low-overhead, modular quantum control structures suited for near-term and long-term quantum computing architectures. The proposed circuit is simulated using the Quirk online tool, and the result confirms the accuracy of the design. This design achieves an average 35% improvement in T-Count without any constant input, compared to its counterpart, respectively.
Quantum Arithmetic Logic Units (ALUs) serve as critical components in quantum processors, enabling both arithmetic and logical operations on qubits. However, the fragile nature of quantum systems makes them susceptible to errors and decoherence, necessitating fault-tolerant designs. In this work, we propose a fault-tolerant quantum ALU architecture constructed using the Clifford+ T gate set, which is widely recognized for its compatibility with error-correcting codes. The proposed design minimizes quantum resource overhead while maintaining computational accuracy under fault-prone conditions. Notably, the architecture requires zero ancilla and generates a single garbage output, optimizing the qubit space. Performance evaluations demonstrate significant improvements, achieving a 31.8% reduction in T-count and a 33.3% reduction in T-depth compared to existing designs. These enhancements contribute to more efficient and reliable quantum computation, paving the way for scalable quantum processor development.
In recent decades, quantum computing has witnessed remarkable progress, achieved through various advancements across the technology stack, such as quantum error-correcting codes and quantum algorithms. It is noteworthy that several promising algorithms incorporate quantum arithmetic circuits as fundamental building blocks. However, the inherent properties of quantum circuits challenge the efficiency of quantum arithmetic circuits, prompting creative solutions. While several quantum arithmetic circuits have been proposed, there is still a substantial gap in quantum arithmetic circuits optimization. For example, methods for integrating classical techniques such as high radix strategy into quantum designs still remain underexplored, highlighting a significant space for further advancement. This thesis aims to improve the performance of quantum arithmetic designs by integrating classical arithmetic circuit design techniques. Specifically, this thesis contains the following research: (1) The utilization of classical higher radix strategy to enhance quantum addition, reducing overall cost by lowering T-depth and T-count. The proposed design outperforms existing quantum carry-lookahead adders. (2) The application of Ling structure, achieving a reduced Toffoli-depth of 4log(n/2). (3) The exploration of the Kogge-Stone architecture, resulting in the lowest Toffoli-depth of log(n) for quantum adders. (4) The development of an efficient modular addition framework using carry-save architecture, demonstrating a 33.3% improvement in Toffoli depth compared to existing designs. (5) The design of an optimized quantum non-restoring divider framework. (6) A comprehensive overview of current advancements in quantum arithmetic designs, offering insights into potential research directions. These proposed designs are mapped to real-world quantum hardware architectures, including Noisy Intermediate-Scale Quantum systems, to validate their functionality and evaluate efficiency. Their applications in quantum machine learning and cryptography further underscore the broader impact of these improvements. Overall, this thesis makes significant advancements in reducing quantum circuit depth and improving resource efficiency, contributing to the development of scalable and efficient large-scale quantum circuits. By adapting classical design strategies to quantum circuits, it not only enhances various quantum circuit designs but also fosters further exploration at the intersection of classical and quantum computing.
Quantum arithmetic operations play a vital role in modern quantum computing applications such as cryptography, signal processing, and large-scale scientific computation. However, conventional quantum multiplication architectures often suffer from high computational complexity, increased Toffoli depth, and excessive T gate consumption, which limit their practical implementation on scalable quantum hardware. This paper presents an optimized distributed quantum multiplication framework based on the Residue Number System (RNS) to improve computational efficiency and scalability. The proposed approach divides large multiplication tasks into multiple modular arithmetic operations that are executed independently across distributed quantum processing units. A Quantum Diminished-1 Modulo (2ⁿ+1) multiplier is incorporated as the fundamental computational block to achieve faster modular multiplication with reduced gate complexity. Performance analysis is carried out for quantum outputs ranging from 6 to 16 qubits and compared with traditional quantum multiplication methods. Experimental results demonstrate significant improvements in resource optimization, including reduced Toffoli depth, minimized T gate utilization, and enhanced execution speed. The proposed framework provides a scalable and efficient solution for next-generation distributed quantum arithmetic systems and supports the development of practical large-scale quantum computing architectures.
Abstract \noindent Efficient quantum arithmetic operations are essential building blocks for complex quantum algorithms, yet few theoretical designs have been implemented in practical quantum programming frameworks. This paper presents the first complete implementation of the T-count optimized non-restoring quantum square root algorithm using the Qrisp quantum programming framework. The algorithm offers better resource efficiency compared to alternative methods, achieving reduced T-count and qubit requirements while avoiding garbage output. Our implementation validates the theoretical resource estimates, confirming a T-count of 14n−14 and a T-depth of 5n+3 for n-bit inputs. The modular design approach enabled by Qrisp allows the construction of reusable components, including reversible adders, subtractors, and conditional logic blocks built from fundamental quantum gates. The three-stage algorithm, comprising initial subtraction, iterative conditional addition/subtraction, and remainder restoration, is successfully translated from algorithmic description to executable quantum code. Experimental validation across multiple test cases confirms the correctness, with the circuit producing accurate integer square roots and remainders. This work demonstrates the practical realizability of resource-optimized quantum arithmetic algorithms and establishes a foundation for implementing different arithmetic operations in modern quantum programming frameworks.
Modular arithmetic is central to quantum algorithms for cryptographic problems, including Shor's algorithm and Grover-based cryptanalysis, with modular reduction contributing substantially to circuit cost. Pseudo-Mersenne moduli q=2n−c allow classical Crandall reduction to replace division with folding and constant arithmetic, providing a structural opportunity for more efficient quantum modular reduction than Barrett reduction. We translate this advantage into a reversible quantum setting by deriving explicit folding and normalization conditions for 2n-bit inputs. To the best of our knowledge, this constitutes the first exact reversible quantum circuit formulation of Crandall reduction. Based on this formulation, we develop two variants: Crandall reduction-1 is designed to minimize execution cost through one-step normalization, whereas Crandall reduction-2 uses two-step normalization to support a wider range of c with limited overhead. Logical resource estimates show that both variants require fewer qubits and lower T-count and T-depth than optimized folding Barrett reduction. At n=10, Crandall reduction-1 reduces both T-count and T-depth by approximately 46.9% relative to optimized folding Barrett reduction. Surface-code analysis further shows that, at n=20 under the Sparse Blossom decoder, the estimated runtimes of the two variants are 30.05 ms and 35.39 ms, respectively, compared with 53.77 ms for optimized folding Barrett reduction. These results demonstrate the practical value of exploiting modulus-specific arithmetic structure in fault-tolerant quantum circuit design.