A key component of quantum algorithms is the efficient multiplication of quantum states; nevertheless, the scalability of traditional quantum multipliers on quantum hardware is frequently limited by high Toffoli depth and excessive T gate utilization. This research introduces a distributed quantum multiplication framework based on the Residue Number System (RNS) that performs numerous quantum modulo multiplication operations across different quantum processors or computational tasks. We present a Quantum Diminished-1 Modulo (2⋅+1) Multiplier inside this framework, which is a crucial element that improves the effectiveness of RNS-based distributed multiplication. For outputs between 6 and 16 qubits, we present a thorough examination of the quantum resource requirements and contrast the suggested method with a traditional non-distributed quantum multiplier. The results underscore the promise of the suggested strategy for scalable and resource-efficient quantum arithmetic, showing reductions of up to 46.02% in Toffoli depth and 34.48% to 86.25% in T gate count.
Quantum arithmetic operations play a vital role in modern quantum computing applications such as cryptography, signal processing, and large-scale scientific computation. However, conventional quantum multiplication architectures often suffer from high computational complexity, increased Toffoli depth, and excessive T gate consumption, which limit their practical implementation on scalable quantum hardware. This paper presents an optimized distributed quantum multiplication framework based on the Residue Number System (RNS) to improve computational efficiency and scalability. The proposed approach divides large multiplication tasks into multiple modular arithmetic operations that are executed independently across distributed quantum processing units. A Quantum Diminished-1 Modulo (2ⁿ+1) multiplier is incorporated as the fundamental computational block to achieve faster modular multiplication with reduced gate complexity. Performance analysis is carried out for quantum outputs ranging from 6 to 16 qubits and compared with traditional quantum multiplication methods. Experimental results demonstrate significant improvements in resource optimization, including reduced Toffoli depth, minimized T gate utilization, and enhanced execution speed. The proposed framework provides a scalable and efficient solution for next-generation distributed quantum arithmetic systems and supports the development of practical large-scale quantum computing architectures.
Quantum Arithmetic faces limitations such as noise and resource constraints in the current Noisy Intermediate Scale Quantum (NISQ) era quantum computers. We propose using Distributed Quantum Computing (DQC) to overcome these limitations by substituting a higher depth quantum addition circuit with Residue Number System (RNS) based quantum modulo adders. The RNS-based distributed quantum addition circuits possess lower depth and are distributed across multiple quantum computers/jobs, resulting in higher noise resilience. We propose the Quantum Superior Modulo Addition based on RNS Tool (QSMART), which can generate RNS sets of quantum adders based on multiple factors such as depth, range, and efficiency. We also propose a novel design of Quantum Diminished-1 Modulo (2n+ 1) Adder (QDMA), which forms a crucial part of RNS-based distributed quantum addition and the QSMART tool. We demonstrate the higher noise resilience of the Residue Number System (RNS) based distributed quantum addition by conducting simulations modeling Quantinuum's HI ion trap-based quantum computer. Our simulations demonstrate that RNS-based distributed quantum addition has 11.36% to 133.15% higher output probability over 6-bit to 10-bit non-distributed quantum full adders, indicating higher noise fidelity. Furthermore, we present a scalable way of achieving distributed quantum addition higher than limited otherwise by the 20-qubit range of Quantinuum HI.
Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2k, 2p-1}. Modulo 2n-1, 2n, and 2n+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2n-1, 2n+k, 2n+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.
Quantum modular adders are one of the most fundamental yet versatile quantum computation operations. They help implement functions of higher complexity, such as subtraction and multiplication, which are used in applications such as quantum cryptanalysis, quantum image processing, and securing communication. To the best of our knowledge, there is no existing design of quantum modulo
(2n+1) adder. In this work, we propose four quantum adders targeted specifically for modulo
(2n+1) addition. These adders can provide both regular and modulo
(2n+1) sum concurrently, enhancing their application in residue number system based arithmetic. Our first design, QMA1, is a novel quantum modulo
(2n+1) adder. The second proposed adder, QMA2, optimizes the utilization of quantum gates within the QMA1, resulting in 37.5% reduced CNOT gate count, 46.15% reduced CNOT depth, and 26.5% decrease in both Toffoli gates and depth. We propose a third adder QMA3 that uses zero resets, a dynamic circuits based feature that reuses qubits, leading to 25% savings in qubit count. Our fourth design, QMA4, demonstrates the benefit of incorporating additional zero resets to achieve a purer zero state, reducing quantum state preparation errors. Notably, we conducted experiments using 5-qubit configurations of the proposed modulo
(2n+1) adders on the IBM Washington, a 127-qubit quantum computer based on the Eagle R1 architecture, to demonstrate a 28.8% reduction in QMA1's error of which: (i) 18.63% error reduction happens due to gate and depth reduction in QMA2, and (ii) 2.53% drop in error due to qubit reduction in QMA3, and (iii) 7.64% error decreased due to application of additional zero resets in QMA4.
Quantum modular adders are one of the most fundamental yet versatile quantum computation operations. They help implement the functions of higher complexity, such as subtraction and multiplication, which are used in applications, such as quantum cryptanalysis, quantum image processing, and securing communication. To the best of our knowledge, there is no existing design of quantum modulo (
2n+1) adder (QMA). In this work, we propose four quantum adders targeted specifically for modulo (
2n+1) addition. These adders can provide both regular and modulo (
2n+1) sum concurrently, enhancing their application in residue number system-based arithmetic. Our first design, QMA1, is a novel quantum modulo (
2n+1) adder. The second proposed adder, QMA2, optimizes the utilization of quantum gates within the QMA1, resulting in 37.5% reduced CNOT gate count, 46.15% reduced CNOT depth, and 26.5% decrease in both Toffoli gates and depth. We propose a third adder QMA3 that uses zero resets, a dynamic circuits-based feature that reuses qubits, leading to 25% savings in qubit count. Our fourth design, QMA4, demonstrates the benefit of incorporating additional zero resets to achieve a purer
∣0$\rangle $state, reducing quantum state preparation errors. Notably, we conducted experiments using 5-qubit configurations of the proposed modulo (
2n+1) adders on the IBM Washington, a 127-qubit quantum computer based on the Eagle R1 architecture, to demonstrate a 28.8% reduction in QMA1’s error of which do the following: 1) 18.63% error reduction happens due to gate/depth reduction in QMA2; 2) 2.53% drop in error due to qubit reduction in QMA3; and 3) 7.64% error decreased due to application of additional zero resets in QMA4.