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International Conference on Electrical and Computer Engineering (ICECE)

Reversible multipliers: Decreasing the depth of the circuit

Fateme Naderpour, Abbas Vafaei

Published Jan 1, 2008• 21 citations
Publisher

Abstract

There are many arithmetic operations which are performed, on a computer arithmetic unit, through the use of multipliers (e.g., exponential and trigonometric functions). Consequently, optimized multipliers are on demand while designing an arithmetic unit. On the other hand, given the advent of quantum computer and reversible logic, design and implementation of digital circuits in this logic has gained popularity. In reversible circuit design, decreasing three parameters is of interest: quantum cost, depth of the circuit and the number of garbage outputs. In this paper, we propose a novel reversible multiplier with the aim of decreasing the depth of the circuit while neither scarifying any extra quantum cost nor garbage outputs. The partial products, as is the case for prior works, are generated in parallel using Peres gates and thereafter a reversible multi-operand adder consisting of reversible full-adders and half-adders produces the final product.

DOI
10.1109/icece.2008.4769222

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There are many arithmetic operations which are performed, on a computer arithmetic unit, through the use of multipliers (e.g., exponential and trigonometric functions). Consequently, optimized multipliers are on demand while designing an arithmetic unit. On the other hand, given the advent of quantum computer and reversible logic, design and implementation of digital circuits in this logic has gained popularity. In reversible circuit design, decreasing three parameters is of interest: quantum cost, depth of the circuit and the number of garbage outputs. In this paper, we propose a novel reversible multiplier with the aim of decreasing the depth of the circuit while neither scarifying any extra quantum cost nor garbage outputs. The partial products, as is the case for prior works, are generated in parallel using Peres gates and thereafter a reversible multi-operand adder consisting of reversible full-adders and half-adders produces the final product.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
Reversible logic plays a crucial role in advancing future VLSI and quantum computing, where the optimization of design parameters like quantum cost, garbage outputs, and circuit complexity is essential. This paper introduces the design and implementation of an efficient 4×4 reversible multiplier on FPGA using Peres and TSG gates. The proposed architecture results in a 31.7 % reduction in quantum cost and enhances TRLIC by up to 30.6% compared to previous designs, while also decreasing garbage outputs and constant inputs. The design has been modeled, simulated, and validated on FPGA to verify its practical viability. Findings indicate that the proposed multiplier strikes a good balance among important parameters, surpassing traditional reversible multipliers in terms of efficiency and scalability. This positions it as a promising option for incorporation into low-power VLSI circuits and quantum arithmetic systems.
Reversible logic is one of the stepping stones in low power circuit design. Due to low power consumption and minimum bit loss features, future quantum computing devices are estimated to be reversible. Compared to addition, multiplication is a step further in the ladder of abstraction. It is the manifestation of a pattern generation system capable of representing 3-D patterns and transforming them by rotation, projection, reflection etc. The use of reversible logic in this field can reduce the wastage of energy, power and improve many factors. In this paper, an efficient multiplication algorithm has been proposed which is a modification of conventional shift-and-add multiplication method. Implementing proposed algorithm two reversible multiplier circuit has been proposed. For producing partial product, Peres gate has been used for the first design and Toffoli gate for the second design. Both of the circuits use Peres gate as Half-Adder and HNG gate as Full-Adder for addition of partial products. The first design is improved radically in terms of quantum cost, delay and the second design is notably improved in terms of transistor count and hardware complexity compared to the existing best known multipliers.
Quantum arithmetic must be built from reversible logic components. This is the driving force for the proposed novel 3/spl times/3 reversible gate termed TKS gate having two of its outputs working as 2:1 multiplexer. The proposed TKS gate is used to design a reversible half adder and is further used to design multiplexer based reversible full adder. The multiplexer based full adder is further used to design reversible 4/spl times/4 Array and modified Baugh Wooley multipliers. A novel 4/spl times/4 multiplier architecture with reversible logic is also proposed in which the partial products can be generated in parallel and their additions are reduced to logarithmic steps. In the proposed multiplier, all the operations are decomposed into levels, thereby significantly reducing the power consumption through a control circuitry which will switch off those levels which are not active. Thus, this work provides the initial threshold to building of complex systems which can execute more complicated operations. The reversible circuits designed and proposed in this paper form the basis for an ALU of a primitive quantum CPU.
In almost all the Digital Signal Processing (DSP) applications, the vital operations involve multiplications and accumulations. Consequently, there is a demand for dedicated hardware in processors to enhance the speed with which these multiplications and accumulations are performed. In the present world of irreversible circuits, the Multiply Accumulate Unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the Accumulator all in a single clock cycle. On the other hand, implementation of digital circuits in reversible logic is gaining popularity with the arrival of quantum computing and reversible logic. In this paper, we propose a novel Reversible Multiply Accumulate (MAC) unit. We also build a Reversible Vedic MAC unit and compare various possible implementations of the reversible MAC unit in terms of Quantum Cost, number of Garbage Outputs and Depth.
Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.