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IETE Journal of Research

A Novel Design of a Multiplier Using Reversible Ternary Gates

Mohammad Mehdi Panahi, Omid Hashemipour, Keivan Navi

Published Jan 30, 2019• 21 citations
Publisher

Abstract

Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.

DOI
10.1080/03772063.2019.1567274

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Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.
The designs using ternary logic exploit its logarithmic reduction in the number of qudits compared with the binary circuits. In this paper, we propose quantum ternary multiplication gate. We term it as QTMG. Then we present the symbol and the realization of QTMG. Researchers will be able to use this gate as well as its symbol and realizations in their future studies. We also present a new realization of ternary Toffoli gate in specific state. Moreover, in this paper, we propose 1-qutrit multiplier circuit. The symbol and the realization of the proposed 1-qutrit multiplier circuit are also provided. Afterward, we proposed ternary partial products generation circuit (TPPG) and summation network circuit in order to design quantum ternary 2-qutrit multiplier circuit. Overall, the proposed design of QTMG in this paper is suggested for the first time. In addition, the proposed realization of ternary Toffoli gate, TPPG, summation network and 2-qutrit multiplier circuits are compared with the existing designs and the improvements are reported. The proposed gate and circuits are realized using macro-level ternary gates which are built on the top of the ion-trap realizable 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.
Reversible ternary circuit design has attracted considerable attention because ternary logic can reduce interconnection ‎complexity relative to binary logic and is compatible with emerging quantum-computing and nanotechnology platforms. This ‎study proposes a reversible 2-trit ternary parallel adder with a quantum cost of 23, one constant input, and three garbage ‎outputs. Compared with previously reported counterparts, the proposed adder requires lower quantum cost and fewer ‎constant inputs and garbage outputs. Based on this adder, a reversible arithmetic unit is developed for two 2-trit unsigned ‎ternary numbers. The unit performs six arithmetic operations: A+B, A−B, A+1, A−1, A+B+1, and A−B−1. The unsigned inputs ‎and outputs are represented within the decimal range from 0 to 8. A reversible arithmetic unit for two signed 2-trit ternary ‎numbers is also proposed. This circuit has a quantum cost of 32 and requires only one constant input. It performs the same six ‎arithmetic operations using the 3’s-complement representation over the range from −4 to +4. In addition, a new reversible ‎overflow detection module is introduced for signed addition and subtraction. By integrating this module with the proposed ‎signed arithmetic unit, a complete reversible ternary arithmetic circuit with overflow-detection capability is obtained. All ‎proposed circuits are constructed using 1-qutrit shift gates and 2-qutrit Muthukrishnan–Stroud gates, which are primitive ‎ternary gates suitable for implementation in ion-trap quantum-computing technology.‎
Multiple-valued logic is a promising choice for future computer technologies, which provides a set of advantages comparing to binary circuits. We have developed an adaptive genetic algorithm for ternary reversible circuits using Muthukrishnan-Stroud gates. The method for chromosomes coding, as well as a reasonable choice of algorithm parameters, allowed obtaining circuits for ternary arithmetic devices, which are better than other known methods in terms of quantum cost, delay time and amount of input ancillary and output garbage qutrits. Based on our realization of ternary parallel full-adder we synthesized reversible ternary parallel adder/subtractor, which has better parameters over the previously reported devices.
Reversible logic is one of the stepping stones in low power circuit design. Due to low power consumption and minimum bit loss features, future quantum computing devices are estimated to be reversible. Compared to addition, multiplication is a step further in the ladder of abstraction. It is the manifestation of a pattern generation system capable of representing 3-D patterns and transforming them by rotation, projection, reflection etc. The use of reversible logic in this field can reduce the wastage of energy, power and improve many factors. In this paper, an efficient multiplication algorithm has been proposed which is a modification of conventional shift-and-add multiplication method. Implementing proposed algorithm two reversible multiplier circuit has been proposed. For producing partial product, Peres gate has been used for the first design and Toffoli gate for the second design. Both of the circuits use Peres gate as Half-Adder and HNG gate as Full-Adder for addition of partial products. The first design is improved radically in terms of quantum cost, delay and the second design is notably improved in terms of transistor count and hardware complexity compared to the existing best known multipliers.
Typical methods of quantum/reversible synthesis are based on using the binary character of quantum computing.However, multi-valued logic is a promising choice for future computer technologies, given a set of advantages when comparing to binary circuits.In this work, we have developed a genetic algorithm-based synthesis of ternary reversible circuits using Muthukrishnan-Stroud gates.The method for chromosomes coding that we present, as well as a judicious choice of algorithm parameters, allowed obtaining circuits for half-adder and full adder which are better than other published methods in terms of cost, delay times and amount of input ancillary bits.A structure of the circuits is analyzed in details, based on their decomposition.
The ternary quantum circuit is very useful in arithmetic and logic operations. This circuit has several advantages as it reduces power dissipation, step time, etc. Adder circuit is the main block of various computing units and for several other complex computer designs. In this current paper, we have used generalized ternary gate (GTG) and reversible gates for the synthesis of reversible half adder and a full adder circuits. The presented designs offer reduced constant inputs and less quantum cost, compared to existing designs. Our proposed design allows a reduction of 40% of the cost and 25% of the number of gates used.