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IEEE International Conference on Data Stream Mining & Processing (DSMP)

New design of reversible/quantum devices for ternary arithmetic

Zhengbing Hu, V. G. Deı̆buk

Published Aug 1, 2016• 2 citations
Publisher

Abstract

Multiple-valued logic is a promising choice for future computer technologies, which provides a set of advantages comparing to binary circuits. We have developed an adaptive genetic algorithm for ternary reversible circuits using Muthukrishnan-Stroud gates. The method for chromosomes coding, as well as a reasonable choice of algorithm parameters, allowed obtaining circuits for ternary arithmetic devices, which are better than other known methods in terms of quantum cost, delay time and amount of input ancillary and output garbage qutrits. Based on our realization of ternary parallel full-adder we synthesized reversible ternary parallel adder/subtractor, which has better parameters over the previously reported devices.

DOI
10.1109/dsmp.2016.7583512

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Multiple-valued logic is a promising choice for future computer technologies, which provides a set of advantages comparing to binary circuits. We have developed an adaptive genetic algorithm for ternary reversible circuits using Muthukrishnan-Stroud gates. The method for chromosomes coding, as well as a reasonable choice of algorithm parameters, allowed obtaining circuits for ternary arithmetic devices, which are better than other known methods in terms of quantum cost, delay time and amount of input ancillary and output garbage qutrits. Based on our realization of ternary parallel full-adder we synthesized reversible ternary parallel adder/subtractor, which has better parameters over the previously reported devices.
Typical methods of quantum/reversible synthesis are based on using the binary character of quantum computing.However, multi-valued logic is a promising choice for future computer technologies, given a set of advantages when comparing to binary circuits.In this work, we have developed a genetic algorithm-based synthesis of ternary reversible circuits using Muthukrishnan-Stroud gates.The method for chromosomes coding that we present, as well as a judicious choice of algorithm parameters, allowed obtaining circuits for half-adder and full adder which are better than other published methods in terms of cost, delay times and amount of input ancillary bits.A structure of the circuits is analyzed in details, based on their decomposition.
Multiple-valued logic is a promising choice for future computer technologies, which provides a set of advantages comparing to binary circuits. In this paper, we have developed a genetic algorithm-based synthesis of ternary reversible circuits using Muthukrishnan-Stroud gates. The method for chromosomes coding, as well as a reasonable choice of algorithm parameters, allowed obtaining circuits for ternary Toffoli and modified Fredkin gates, which are better than other published methods in terms of quantum cost, delay times and amount of input ancillary and output garbage qutrits.
Methods of quantum/reversible logic synthesis are based on the use of the binary nature of quantum computing. However, multiple-valued logic is a promising choice for future quantum computer technology due to a number of advantages over binary circuits. In this paper we have developed a synthesis of ternary reversible circuits based on Muthukrishnan-Stroud gates using a genetic algorithm. The method of coding chromosome is presented, and well-grounded choice of algorithm parameters allowed obtaining better circuit schemes of one- and n-qutrit ternary comparators compared with other methods. These parameters are quantum cost of received reversible devices, delay time and number of constant input (ancilla) lines. Proposed implementation of the genetic algorithm has led to reducing of the device delay time and the number of ancilla qutrits to 1 and 2n-1 for one- and n-qutrits full comparators, respectively. For designing of n-qutrit comparator we have introduced a complementary device which compares output functions of 1-qutrit comparators.
Reversible ternary circuit design has attracted considerable attention because ternary logic can reduce interconnection ‎complexity relative to binary logic and is compatible with emerging quantum-computing and nanotechnology platforms. This ‎study proposes a reversible 2-trit ternary parallel adder with a quantum cost of 23, one constant input, and three garbage ‎outputs. Compared with previously reported counterparts, the proposed adder requires lower quantum cost and fewer ‎constant inputs and garbage outputs. Based on this adder, a reversible arithmetic unit is developed for two 2-trit unsigned ‎ternary numbers. The unit performs six arithmetic operations: A+B, A−B, A+1, A−1, A+B+1, and A−B−1. The unsigned inputs ‎and outputs are represented within the decimal range from 0 to 8. A reversible arithmetic unit for two signed 2-trit ternary ‎numbers is also proposed. This circuit has a quantum cost of 32 and requires only one constant input. It performs the same six ‎arithmetic operations using the 3’s-complement representation over the range from −4 to +4. In addition, a new reversible ‎overflow detection module is introduced for signed addition and subtraction. By integrating this module with the proposed ‎signed arithmetic unit, a complete reversible ternary arithmetic circuit with overflow-detection capability is obtained. All ‎proposed circuits are constructed using 1-qutrit shift gates and 2-qutrit Muthukrishnan–Stroud gates, which are primitive ‎ternary gates suitable for implementation in ion-trap quantum-computing technology.‎
Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.