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International Journal of Fundamental Physical Sciences

Designing a New Ternary Arithmetic Unit with Overflow Detection Using Reversible Ternary

Mohammad Mehdi Panahi

Published Jun 30, 2026• 0 citations

Abstract

Reversible ternary circuit design has attracted considerable attention because ternary logic can reduce interconnection ‎complexity relative to binary logic and is compatible with emerging quantum-computing and nanotechnology platforms. This ‎study proposes a reversible 2-trit ternary parallel adder with a quantum cost of 23, one constant input, and three garbage ‎outputs. Compared with previously reported counterparts, the proposed adder requires lower quantum cost and fewer ‎constant inputs and garbage outputs. Based on this adder, a reversible arithmetic unit is developed for two 2-trit unsigned ‎ternary numbers. The unit performs six arithmetic operations: A+B, A−B, A+1, A−1, A+B+1, and A−B−1. The unsigned inputs ‎and outputs are represented within the decimal range from 0 to 8. A reversible arithmetic unit for two signed 2-trit ternary ‎numbers is also proposed. This circuit has a quantum cost of 32 and requires only one constant input. It performs the same six ‎arithmetic operations using the 3’s-complement representation over the range from −4 to +4. In addition, a new reversible ‎overflow detection module is introduced for signed addition and subtraction. By integrating this module with the proposed ‎signed arithmetic unit, a complete reversible ternary arithmetic circuit with overflow-detection capability is obtained. All ‎proposed circuits are constructed using 1-qutrit shift gates and 2-qutrit Muthukrishnan–Stroud gates, which are primitive ‎ternary gates suitable for implementation in ion-trap quantum-computing technology.‎

DOI: 10.14331/ijfps.2026.330185

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