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IEEE Transactions on Applied Superconductivity

Design and fabrication of an adder circuit in the extended phase-mode logic

Takeshi Onomi, Takashi Yamashita, Yoshinao Mizugaki, Kiyotaka Nakajima

Published Jun 1, 1997• 3 citations
Publisher

Abstract

We present the design and the fabrication of an adder circuit in the extended phase-mode logic family. The phase-mode logic is a single flux quantum (SFQ) logic which utilizes an SFQ as an information bit carrier. The single-bit adder circuit is made up of an INHIBIT gate which is the basic device of the phase-mode logic. The circuit has been designed and fabricated using Nb/AlO/sub x//Nb Josephson junctions with Josephson critical current density of 1.0 kA/cm/sup 2/. In order to confirm the circuit operation, the fabricated adder circuit has been tested at low speed. For investigating the possibility of a high-frequency operation, dc voltages generated by fluxon pulse trains have been measured. From the Josephson voltage-frequency relation, the result shows that the circuit has potential to complete the carry operation within 20 psec.

DOI
10.1109/77.622004

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We present the design and the fabrication of an adder circuit in the extended phase-mode logic family. The phase-mode logic is a single flux quantum (SFQ) logic which utilizes an SFQ as an information bit carrier. The single-bit adder circuit is made up of an INHIBIT gate which is the basic device of the phase-mode logic. The circuit has been designed and fabricated using Nb/AlO/sub x//Nb Josephson junctions with Josephson critical current density of 1.0 kA/cm/sup 2/. In order to confirm the circuit operation, the fabricated adder circuit has been tested at low speed. For investigating the possibility of a high-frequency operation, dc voltages generated by fluxon pulse trains have been measured. From the Josephson voltage-frequency relation, the result shows that the circuit has potential to complete the carry operation within 20 psec.
We present extended phase-mode logic (EPL) circuits which have resistive ground contact. The phase-mode logic utilizes magnetic flux-transfer and is based on pulse propagation, i.e., it is one of single flux quantum systems. The proposed logic circuits of the EPL family can have the same ground reference, contrary to the original phase-mode circuits, Therefore, it is possible to couple different EPL elements on a single ground reference. Basic components of the EPL family (a phase-conserving branch, a phase-distributing branch, and an INHIBIT gate controlled by fluxon) are presented. The phase-distributing branch and the INHIBIT gate have been fabricated using a Nb/AlO/sub x//Nb Josephson-junction technology and tested. A fan-in operation of the phase-distributing branch and the first full operation of the INHIBIT gate are successfully demonstrated. As an example of the EPL logic circuits consisting of plural gates on a single ground reference, a simulation of a 2-bit full adder circuit is also presented.>
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We report the preliminary designs and the experimental results of high-speed digital processing elements based on phase-mode logic circuits. The core cell of these elements is a bit-serial adder cell consisting of the ICF gate which is the basic gate of phase-mode logic. Our main target is the application of the logic circuits to Digital Signal Processing. The basic arithmetic operations of DSP are a multiplication and an addition. Basic concept of the phase-mode pipelined parallel multiplier has been proposed previously. We design a 2 /spl times/ 2 AND array block and a 2-bit ripple-carry adder for the primitive parallel pipelined multiplier and also a 2-bit subtractor with a pipelined structure. These processing elements have been fabricated using NEC standard 2.5 kA/cm/sup 2/ Nb/AlOx/Nb process. The low-speed test results of these elements show correct operations. Numerical simulations show that a carry save adder (a 2-bit ripple carry adder) can operate over 10 GHz. We also discuss the prospects of large-scale SFQ DSP based on Nb junction technology.
100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2{\rm kA/cm}^{2}kA/cm2 Niobium Process
This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.
We report low-power single-flux-quantum (SFQ) circuits fabricated with a lowered critical current density process and low-voltage design. We selected 250 A/cm2^{2}2to obtain 2–10 μA Josephson junctions (JJs) easily using conventional facilities. Our numerical simulation shows that the expected operating frequency is 10 GHz and that we can reduce the bias voltage to 0.1–0.5 mV; power consumption can be reduced to around 1 nW per JJ. We newly developed a fabrication process featuring four planarized Nb layers and a Pd resistor layer. We obtained the correct operation of several basic SFQ circuit elements designed with the lowered critical currents to 1/2 of the conventional circuits at 4.2 K. We also evaluated the Josephson junction critical currents, specific capacitance, resistance, and inductance at 3 K and 300 mK. We observed an increase of 7% in the critical currents at 300 mK, while the other parameters were unchanged. We demonstrated a 0.5-mV Josephson transmission line where we lowered the critical currents to 1/10. We expect such low-power SFQ circuits to operate at 20 mK, providing classical, general-purpose digital processing near quantum bits.