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NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

A compact realization of an n-bit quantum carry skip adder circuit with optimal delay

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

Published Jul 1, 2014• 2 citations
Publisher

Abstract

This paper presents the design of a novel n-bit carry skip adder by its core components using quantum logic. The novelty of the proposed adder is that it considers a new design with optimal delay. Moreover, it is the first time in quantum circuit synthesis that the quantum realization of a carry skip adder is shown in terms of quantum gates, power and area, etc. Our proposed quantum multiplexer gate (QMG) and quantum comparison gate (QCG) perfectly operates as a 2-to-1 MUX and a comparison circuit, respectively. Using QMG and QCG as a unit element of construction, we optimize the design of Carry Skip Adder. A generalized architecture of the proposed n-bit adder has also been presented. The comparative study shows that the proposed quantum carry skip adder performs better than the existing carry skip adders with the increasing number of bits; e.g., the proposed 128-bit carry skip adder improves 40.96% on number of quantum gates, 48.19% on delay, 22.22% on garbage outputs and 40.96% on area and power over the existing best one. In addition, we also simulate the proposed adder using Microwind DSCH 3.5 and QuIDDPro software to show the correctness of the circuit.

DOI
10.1109/ahs.2014.6880187

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This paper presents the design of a novel n-bit carry skip adder by its core components using quantum logic. The novelty of the proposed adder is that it considers a new design with optimal delay. Moreover, it is the first time in quantum circuit synthesis that the quantum realization of a carry skip adder is shown in terms of quantum gates, power and area, etc. Our proposed quantum multiplexer gate (QMG) and quantum comparison gate (QCG) perfectly operates as a 2-to-1 MUX and a comparison circuit, respectively. Using QMG and QCG as a unit element of construction, we optimize the design of Carry Skip Adder. A generalized architecture of the proposed n-bit adder has also been presented. The comparative study shows that the proposed quantum carry skip adder performs better than the existing carry skip adders with the increasing number of bits; e.g., the proposed 128-bit carry skip adder improves 40.96% on number of quantum gates, 48.19% on delay, 22.22% on garbage outputs and 40.96% on area and power over the existing best one. In addition, we also simulate the proposed adder using Microwind DSCH 3.5 and QuIDDPro software to show the correctness of the circuit.
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