This paper presents a compact realization of quantum n-to-2ndecoder circuit, where n is the number of input bits. The proposed design of the quantum n-to-2ndecoder circuit shows that it is composed of the quantum 2-to-4 decoder circuit. We present a quantum 2-to-4 decoder circuit using quantum Peres gate and CNOT quantum gates. Finally, we show an algorithm to construct a compact n-to-2nquantum decoder circuit. Our circuit performs better than the existing ones, e.g., the proposed 3-to-8 quantum decoder circuit improves 15.6% on the number of quantum gates, delay, area and power, 66.67% on garbage outputs and 25% on constant inputs than the Existing Design-2. We also simulate the proposed quantum decoder using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
This paper presents a compact realization of quantum n-to-2ndecoder circuit, where n is the number of input bits. The proposed design of the quantum n-to-2ndecoder circuit shows that it is composed of the quantum 2-to-4 decoder circuit. We present a quantum 2-to-4 decoder circuit using quantum Peres gate and CNOT quantum gates. Finally, we show an algorithm to construct a compact n-to-2nquantum decoder circuit. Our circuit performs better than the existing ones, e.g., the proposed 3-to-8 quantum decoder circuit improves 15.6% on the number of quantum gates, delay, area and power, 66.67% on garbage outputs and 25% on constant inputs than the Existing Design-2. We also simulate the proposed quantum decoder using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
In this paper, we propose a reversible quantum 2n_ to-n BCD priority encoder circuit, where n is the number of output bits. The proposed design of the 2n-to-n BCD priority encoder circuit shows that it is composed of quantum circuits for OR operation and quantum NOT gates. We present an algorithm to construct a minimized quantum 2n-to-n BCD priority encoder circuit. A technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. Our circuit performs better than the existing ones in terms of quantum gates, delays, garbage outputs, constant inputs, quantum gate calculation complexity, area and power, e.g., the proposed quantum 8-to-3 BCD priority encoder circuit improves 41.25% on the number of quantum gates, 46.05% on delays, 48% on garbage outputs, 60% on constant inputs and 41.25% on area and power than the existing circuit. We also simulate the proposed quantum BCD priority encoder circuit using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
In this paper, we propose a reversible quantum 2n-to-n BCD priority encoder circuit, where n is the number of output bits. The proposed design of the 2n-to-n BCD priority encoder circuit shows that it is composed of quantum circuits for OR operation and quantum NOT gates. We present an algorithm to construct a minimized quantum 2n-to-n BCD priority encoder circuit. A technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. Our circuit performs better than the existing ones in terms of quantum gates, delays, garbage outputs, constant inputs, quantum gate calculation complexity, area and power, e.g., the proposed quantum 8-to-3 BCD priority encoder circuit improves 41.25% on the number of quantum gates, 46.05% on delays, 48% on garbage outputs, 60% on constant inputs and 41.25% on area and power than the existing circuit. We also simulate the proposed quantum BCD priority encoder circuit using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized 2:4 decoder using reversible logic gate. The proposed reversible circuit is design using existing reversible logic gate, such as reversible NOT gate, Feynman gate and Peres gate. The proposed decoder can be design using one Peres gate, one NOT gate and four Feynman gate. The QC, GO and CI of the proposed 2:4 decoder is 9, 0 and 2. Which is better w.r.t previously reported work. This is the first reversible 2:4 decoder circuit, which has `0' garbage output. The improvement % of QC, GO and CI are 0 - 74.28 %, 100 % and 33.33 - 75 %.
Abstract Decoder is a combinational logic circuit; it changes a code into a collection of signals. Decoder is incredibly important circuit employed in combinational logic. Reversible logic may be a new research area due to its reduction in power dissipation and lots of researchers proposed differing types of approaches to construct a quantum reversible decoder. In this paper we tried to design n to 2n reversible decoder using modified TOFFOLI reversible logic gates. We proposed 1 to 21, 2 to 22 and 3 to 23, 4 to 24 and 5 to 25 reversible decoder and analyzed its lead in respect of quantum cost and garbage output. We tried to propose an algorithm that helps to design n to 2n reversible decoder. All circuit of the decoder are tested by using IBM Quantum Experience circuit composer.
In this paper, we have proposed a quantum cost optimized reversible 2's complement code converter (2SCCC) circuit using existing reversible logic gate. First, we have design a reversible controlled inverter using Feynman gate and then we have design the proposed code converter (2SCCC) circuit using Feynman gate and Peres gate. Finally, we have proposed the design of quantum cost optimized reversible 2's complement code converter. The quantum cost (QC), garbage output (GO), delay and constant input (CI) of the proposed 2's complement code converter circuits are 11, 1, 7 and 1 which is better w. r. t. previously reported results. The improvement % of quantum cost, garbage outputs, delay and constant inputs are 26.66 - 60.71 %, 0 - 92.3 %, 25 - 57.14 % and 0 - 83.33 %.
Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.