Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

2018 IEEE Electron Devices Kolkata Conference (EDKCON)

Quantum Cost Optimized Design of Reversible 2's Complement Code Converter

Heranmoy Maity, Arindam Biswas, Anita Pal, Anup Kumar Bhattacharjee

Published Nov 1, 2018• 3 citations
Publisher

Abstract

In this paper, we have proposed a quantum cost optimized reversible 2's complement code converter (2SCCC) circuit using existing reversible logic gate. First, we have design a reversible controlled inverter using Feynman gate and then we have design the proposed code converter (2SCCC) circuit using Feynman gate and Peres gate. Finally, we have proposed the design of quantum cost optimized reversible 2's complement code converter. The quantum cost (QC), garbage output (GO), delay and constant input (CI) of the proposed 2's complement code converter circuits are 11, 1, 7 and 1 which is better w. r. t. previously reported results. The improvement % of quantum cost, garbage outputs, delay and constant inputs are 26.66 - 60.71 %, 0 - 92.3 %, 25 - 57.14 % and 0 - 83.33 %.

DOI
10.1109/edkcon.2018.8770220

Related papers

Design of Quantum Cost and Delay Optimized Code Converter Using New Reversible Quantum Circuit Block (QCB)

Heranmoy Maity, Sudipta Banerjee, Raton Mistry +8 more

Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50% respectively compared with respect to the latest reported results. Conclusion: So the improvement of QC and delay are very high using QCB.

Micro and Nanosystems•May 2, 2020•3 citations

The Quantum Cost, Garbage Outputs and Constant Input Optimized Implementation of 2:4 Decoder Using Peres Gate

Heranmoy Maity, Arindam Biswas, Anup Kr. Bhattacharjee +1 more

This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized 2:4 decoder using reversible logic gate. The proposed reversible circuit is design using existing reversible logic gate, such as reversible NOT gate, Feynman gate and Peres gate. The proposed decoder can be design using one Peres gate, one NOT gate and four Feynman gate. The QC, GO and CI of the proposed 2:4 decoder is 9, 0 and 2. Which is better w.r.t previously reported work. This is the first reversible 2:4 decoder circuit, which has `0' garbage output. The improvement % of QC, GO and CI are 0 - 74.28 %, 100 % and 33.33 - 75 %.

Devices for Integrated Circuit (DevIC)•Mar 1, 2019•6 citations

Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

Heranmoy Maity, Arindam Biswas, Anita Pal +1 more

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

International Journal of Quantum Information•Oct 1, 2018•8 citations

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

Heranmoy Maity, Arijit Kumar Barik, Arindam Biswas +2 more

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Journal of Circuits Systems and Computers•Feb 14, 2018•16 citations

Design and implementations of new reversible 7’s and 8’s complement code converter for quantum computations

Heranmoy Maity, Gopal Kumar Gupta, Bidrohi Bhattacharjee +3 more

Quantum computing is an extremely promising domain in engineering and technology, primarily because it offers low power consumption and high-speed operation. In this article, the authors proposed the new reversible 7’s and 8’s complement code converter (C-CC) using reversible NOT and Peres gate (PG). The reversible 7’s C-CC designed using only three reversible NOT gates. The Quantum cost (QC), Constant Input (CI), garbage output (GO) and Delay are 3, 0, 0 and 1 respectively. The 8’s C-CC can be designed by adding extra ‘1’ with 7’s Complement code. The 8’s C-CC designed using only one PG and four reversible NOT gates. The QC, CI, GO and delay of the proposed 8’s C-CC is 8, 0, 0 and 1 respectively. The proposed work is verified using IBM Qiskit simulator.

AIP conference proceedings•Jan 1, 2024•13 citations

Design and Development of Cost Optimized Quantum Binary-Coded Decimal Adder using Reversible Logic Gates

Parna Kundu, Mousom Chatterjee, Susmita Biswas +6 more

Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.

ES General•Jan 1, 2025•0 citations
In this paper, we have proposed a quantum cost optimized reversible 2's complement code converter (2SCCC) circuit using existing reversible logic gate. First, we have design a reversible controlled inverter using Feynman gate and then we have design the proposed code converter (2SCCC) circuit using Feynman gate and Peres gate. Finally, we have proposed the design of quantum cost optimized reversible 2's complement code converter. The quantum cost (QC), garbage output (GO), delay and constant input (CI) of the proposed 2's complement code converter circuits are 11, 1, 7 and 1 which is better w. r. t. previously reported results. The improvement % of quantum cost, garbage outputs, delay and constant inputs are 26.66 - 60.71 %, 0 - 92.3 %, 25 - 57.14 % and 0 - 83.33 %.
Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50% respectively compared with respect to the latest reported results. Conclusion: So the improvement of QC and delay are very high using QCB.
This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized 2:4 decoder using reversible logic gate. The proposed reversible circuit is design using existing reversible logic gate, such as reversible NOT gate, Feynman gate and Peres gate. The proposed decoder can be design using one Peres gate, one NOT gate and four Feynman gate. The QC, GO and CI of the proposed 2:4 decoder is 9, 0 and 2. Which is better w.r.t previously reported work. This is the first reversible 2:4 decoder circuit, which has `0' garbage output. The improvement % of QC, GO and CI are 0 - 74.28 %, 100 % and 33.33 - 75 %.
In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.
In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.
Quantum computing is an extremely promising domain in engineering and technology, primarily because it offers low power consumption and high-speed operation. In this article, the authors proposed the new reversible 7’s and 8’s complement code converter (C-CC) using reversible NOT and Peres gate (PG). The reversible 7’s C-CC designed using only three reversible NOT gates. The Quantum cost (QC), Constant Input (CI), garbage output (GO) and Delay are 3, 0, 0 and 1 respectively. The 8’s C-CC can be designed by adding extra ‘1’ with 7’s Complement code. The 8’s C-CC designed using only one PG and four reversible NOT gates. The QC, CI, GO and delay of the proposed 8’s C-CC is 8, 0, 0 and 1 respectively. The proposed work is verified using IBM Qiskit simulator.
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.