Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50% respectively compared with respect to the latest reported results. Conclusion: So the improvement of QC and delay are very high using QCB.
Background: In this article, we have proposed a new reversible quantum circuit block along with the quantum cost (QC), constant input (CI), garbage output (GO) and delay optimized code converterusing quantum circuit block. Method: Initially, new quantum circuit block has been designed and later reversible code converter circuits have been implemented using it. The proposed new quantum blockused to design 2’s complement code converter (2SCCC), cost efficient BCD to Excess-3 code converter (BECC) and can also be used to implement different logic functions. The QC of proposed quantum circuit block is 8. The QC and delay of the proposed 2SCCC is 8 and 1 respectively. Similarly, the QC and delay of the proposed BECC is 11 and 2 respectively. The proposed cost efficient BECC is designed using two NOT gate, one Feynman gate and one new quantum circuit block with QC is 11. Results: The improvement of QC for 2SCCC and BECC are 27.27 % and 21.43% respectively. The improvement of delay for 2SCCC and BECC are 66.67% and 50% respectively compared with respect to the latest reported results. Conclusion: So the improvement of QC and delay are very high using QCB.
In this paper, we have proposed a quantum cost optimized reversible 2's complement code converter (2SCCC) circuit using existing reversible logic gate. First, we have design a reversible controlled inverter using Feynman gate and then we have design the proposed code converter (2SCCC) circuit using Feynman gate and Peres gate. Finally, we have proposed the design of quantum cost optimized reversible 2's complement code converter. The quantum cost (QC), garbage output (GO), delay and constant input (CI) of the proposed 2's complement code converter circuits are 11, 1, 7 and 1 which is better w. r. t. previously reported results. The improvement % of quantum cost, garbage outputs, delay and constant inputs are 26.66 - 60.71 %, 0 - 92.3 %, 25 - 57.14 % and 0 - 83.33 %.
In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.
In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.
In this article, a new quantum reversible circuit or QRC block has been proposed to implement the quantum BCD-to-Excess-3 code converter using Qiskit, which is used to convert quantum BCD code to Excess-3 code. The proposed quantum BCD-to-Excess-3 or QBEC is most important for quantum information processing. It can be used for quantum cryptography, quantum communication etc. The proposed new quantum reversible circuit is also used to realize the different logic functions such as OR, XOR, XNOR, NOR, NAND, NOT and other logic functions. The proposed QRC is represented by quantum implementation with quantum cost 8. The QRC is implemented and verified using IBM Qiskit. The quantum cost, garbage output and delay of the QBEC converter circuit are 8, 1 and 1. The improvement % of quantum cost and delay w.r.t. previously reported results are 27.27% and 50% respectively.
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.
Quantum computing is an extremely promising domain in engineering and technology, primarily because it offers low power consumption and high-speed operation. In this article, the authors proposed the new reversible 7’s and 8’s complement code converter (C-CC) using reversible NOT and Peres gate (PG). The reversible 7’s C-CC designed using only three reversible NOT gates. The Quantum cost (QC), Constant Input (CI), garbage output (GO) and Delay are 3, 0, 0 and 1 respectively. The 8’s C-CC can be designed by adding extra ‘1’ with 7’s Complement code. The 8’s C-CC designed using only one PG and four reversible NOT gates. The QC, CI, GO and delay of the proposed 8’s C-CC is 8, 0, 0 and 1 respectively. The proposed work is verified using IBM Qiskit simulator.