This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized 2:4 decoder using reversible logic gate. The proposed reversible circuit is design using existing reversible logic gate, such as reversible NOT gate, Feynman gate and Peres gate. The proposed decoder can be design using one Peres gate, one NOT gate and four Feynman gate. The QC, GO and CI of the proposed 2:4 decoder is 9, 0 and 2. Which is better w.r.t previously reported work. This is the first reversible 2:4 decoder circuit, which has `0' garbage output. The improvement % of QC, GO and CI are 0 - 74.28 %, 100 % and 33.33 - 75 %.
This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized 2:4 decoder using reversible logic gate. The proposed reversible circuit is design using existing reversible logic gate, such as reversible NOT gate, Feynman gate and Peres gate. The proposed decoder can be design using one Peres gate, one NOT gate and four Feynman gate. The QC, GO and CI of the proposed 2:4 decoder is 9, 0 and 2. Which is better w.r.t previously reported work. This is the first reversible 2:4 decoder circuit, which has `0' garbage output. The improvement % of QC, GO and CI are 0 - 74.28 %, 100 % and 33.33 - 75 %.
In this paper, we have proposed a quantum cost optimized reversible 2's complement code converter (2SCCC) circuit using existing reversible logic gate. First, we have design a reversible controlled inverter using Feynman gate and then we have design the proposed code converter (2SCCC) circuit using Feynman gate and Peres gate. Finally, we have proposed the design of quantum cost optimized reversible 2's complement code converter. The quantum cost (QC), garbage output (GO), delay and constant input (CI) of the proposed 2's complement code converter circuits are 11, 1, 7 and 1 which is better w. r. t. previously reported results. The improvement % of quantum cost, garbage outputs, delay and constant inputs are 26.66 - 60.71 %, 0 - 92.3 %, 25 - 57.14 % and 0 - 83.33 %.
Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.
In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.
Background/Objectives: The objective is to reduce the Quantum Cost (QC), Garbage Output (GO) and Gate Counts in the design of the adder by incorporating the Novel Reversible Gates. Methods/Statistical Analysis: In recent day’s energy dissipation is the major complex problem in circuit designing in order to recede this problem the reversible logic is employed, where the input vectors can be derived from the output vectors and from the output vectors the input vectors can be procured. Using this technique the Quantum Cost, Garbage Outputs and Gate Counts of the design is reduced. Findings: Based on the technique of reversible logic a novel reversible Gates is proposed from that the novel reversible adders have been designed. The novel reversible gates satisfy the property of reversibility and universality which shows the uniqueness of the proposed gates. The comparative analysis have been made with the existing work, the proposed work shows a significant improvement in the design optimization parameters. Application/Improvements: The proposed structures can be employed in the ALU design and in Floating Point Multiplier design. The comparative analysis shows that Number of Gates, Garbage Outputs and Quantum Cost is minimum for the proposed gate based structure rather than conventional one Keywords: Garbage Outputs (GO), QCA, Quantum Cost (QC), Reversibility, Reversible Logic, Universality.
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.
In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.