In this paper, we propose a reversible quantum 2n-to-n BCD priority encoder circuit, where n is the number of output bits. The proposed design of the 2n-to-n BCD priority encoder circuit shows that it is composed of quantum circuits for OR operation and quantum NOT gates. We present an algorithm to construct a minimized quantum 2n-to-n BCD priority encoder circuit. A technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. Our circuit performs better than the existing ones in terms of quantum gates, delays, garbage outputs, constant inputs, quantum gate calculation complexity, area and power, e.g., the proposed quantum 8-to-3 BCD priority encoder circuit improves 41.25% on the number of quantum gates, 46.05% on delays, 48% on garbage outputs, 60% on constant inputs and 41.25% on area and power than the existing circuit. We also simulate the proposed quantum BCD priority encoder circuit using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
In this paper, we propose a reversible quantum 2n-to-n BCD priority encoder circuit, where n is the number of output bits. The proposed design of the 2n-to-n BCD priority encoder circuit shows that it is composed of quantum circuits for OR operation and quantum NOT gates. We present an algorithm to construct a minimized quantum 2n-to-n BCD priority encoder circuit. A technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. Our circuit performs better than the existing ones in terms of quantum gates, delays, garbage outputs, constant inputs, quantum gate calculation complexity, area and power, e.g., the proposed quantum 8-to-3 BCD priority encoder circuit improves 41.25% on the number of quantum gates, 46.05% on delays, 48% on garbage outputs, 60% on constant inputs and 41.25% on area and power than the existing circuit. We also simulate the proposed quantum BCD priority encoder circuit using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
In this paper, we propose a reversible quantum 2n_ to-n BCD priority encoder circuit, where n is the number of output bits. The proposed design of the 2n-to-n BCD priority encoder circuit shows that it is composed of quantum circuits for OR operation and quantum NOT gates. We present an algorithm to construct a minimized quantum 2n-to-n BCD priority encoder circuit. A technique to calculate the quantum gate complexity of quantum circuits has also been proposed in the paper. Our circuit performs better than the existing ones in terms of quantum gates, delays, garbage outputs, constant inputs, quantum gate calculation complexity, area and power, e.g., the proposed quantum 8-to-3 BCD priority encoder circuit improves 41.25% on the number of quantum gates, 46.05% on delays, 48% on garbage outputs, 60% on constant inputs and 41.25% on area and power than the existing circuit. We also simulate the proposed quantum BCD priority encoder circuit using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
This paper presents a compact realization of quantum n-to-2ndecoder circuit, where n is the number of input bits. The proposed design of the quantum n-to-2ndecoder circuit shows that it is composed of the quantum 2-to-4 decoder circuit. We present a quantum 2-to-4 decoder circuit using quantum Peres gate and CNOT quantum gates. Finally, we show an algorithm to construct a compact n-to-2nquantum decoder circuit. Our circuit performs better than the existing ones, e.g., the proposed 3-to-8 quantum decoder circuit improves 15.6% on the number of quantum gates, delay, area and power, 66.67% on garbage outputs and 25% on constant inputs than the Existing Design-2. We also simulate the proposed quantum decoder using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.
In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.
Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.