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Design of n to 2n quantum reversible decoder using Modified Toffoli gate

Sujit Biswas, Rajat Subhra Goswami

Published Jun 16, 2023• 0 citations
Publisher

Abstract

Abstract Decoder is a combinational logic circuit; it changes a code into a collection of signals. Decoder is incredibly important circuit employed in combinational logic. Reversible logic may be a new research area due to its reduction in power dissipation and lots of researchers proposed differing types of approaches to construct a quantum reversible decoder. In this paper we tried to design n to 2n reversible decoder using modified TOFFOLI reversible logic gates. We proposed 1 to 21, 2 to 22 and 3 to 23, 4 to 24 and 5 to 25 reversible decoder and analyzed its lead in respect of quantum cost and garbage output. We tried to propose an algorithm that helps to design n to 2n reversible decoder. All circuit of the decoder are tested by using IBM Quantum Experience circuit composer.

DOI
10.21203/rs.3.rs-3034877/v1

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Abstract Decoder is a combinational logic circuit; it changes a code into a collection of signals. Decoder is incredibly important circuit employed in combinational logic. Reversible logic may be a new research area due to its reduction in power dissipation and lots of researchers proposed differing types of approaches to construct a quantum reversible decoder. In this paper we tried to design n to 2n reversible decoder using modified TOFFOLI reversible logic gates. We proposed 1 to 21, 2 to 22 and 3 to 23, 4 to 24 and 5 to 25 reversible decoder and analyzed its lead in respect of quantum cost and garbage output. We tried to propose an algorithm that helps to design n to 2n reversible decoder. All circuit of the decoder are tested by using IBM Quantum Experience circuit composer.
The technologies like quantum computing, Nanotechnology is emerging due to the greater research in reversible logic. It has the power reduction capability the same mechanism is also having in the quantum computing. Designing a quantum circuit among various combinational circuits the decoder has capability to change binary information of input lines to distinct output lines and also there are many applications where decoder is the main basic component. In this paper a comprehensive introduction of basic gates used to design n to 2nUniversal Quantum decoder, here n represents the no of inputs are mentioned. The proposed 2:4 decoder circuit is designed using a universal reversible Fredkin gates and Feynman gate. The proposed work is simulated using IBM Quantum Composer. In comparison to existing quantum decoders the proposed decoder design has optimum values in all the parameters considered.
This paper presents a compact realization of quantum n-to-2ndecoder circuit, where n is the number of input bits. The proposed design of the quantum n-to-2ndecoder circuit shows that it is composed of the quantum 2-to-4 decoder circuit. We present a quantum 2-to-4 decoder circuit using quantum Peres gate and CNOT quantum gates. Finally, we show an algorithm to construct a compact n-to-2nquantum decoder circuit. Our circuit performs better than the existing ones, e.g., the proposed 3-to-8 quantum decoder circuit improves 15.6% on the number of quantum gates, delay, area and power, 66.67% on garbage outputs and 25% on constant inputs than the Existing Design-2. We also simulate the proposed quantum decoder using Microwind DSCH 2.7 which shows the functional correctness of the circuit.
Reversible logic is a circuit which has the ability to reduce the power dissipation. This type of logic circuit is used for the process of running the system both forward and backward.One of the main advantages of using any reversible logic is to get back the original data and to reduce the garbage output. Logic synthesis based on the Kronecker Functional Decision Diagram (KFDD) are generated for different reversible cascade methods both complemented and uncomplemented edge by using different reversible gates such as the CNOT (Controlled NOT), NOT, Toffoli gates, Peres gates, etc., and implemented in a quantum processor. In order to reduce the qubits which in turn reduces the quantum cost, it is implemented using reversible logic synthesis in KFDD method.The proposed method shows the implementation of these reversible circuits in an IBM quantum computer to find the probabilities, as it gives less quantum cost and also consumes less time when compared to other decision diagram. Reversible logic finds a wide range of applications in quantum computing and also in areas which deals with the low power design.This paper presents the implementation of KFDD using quantum circuits in IBM Quantum (IBM-Q) processor using different reversible logics and the output is discussed.
Reversible logic has received great attention in last few years as it dissipates very low power. This paper presents the reversible logic synthesis for the n-to-2nfault tolerant decoder, where n is the number of data bits. A low cost 6 × 6 reversible gate is proposed to design a 2-to-4 reversible fault tolerant decoder which has least delay. An algorithm is derived to construct higher bit order decoder. Theoretical explanations certify the novelty of the proposed design. Comparing with previous works, the proposed design shows significant reduction in gate count, quantum cost and delay, which are 66.66%, 8.33%, 16.66%, respectively, with respect to the corresponding metrics of the best existing 2-to-4 fault tolerant decoder. Area and power consumption of the proposed circuit are also estimated.
Abstract Reversible gates have been one of the emerging research areas in these days. The reversible gates have several applications in the fields of low power CMOS, DNA computing, optical, nanotechnology etc. Quantum computing is one of the fastest and upcoming nanotechnologies that can implement the digital logical circuits using reversible logic gates. In this paper, CNOT, TOFFOLI, FREDKIN and PERES reversible logic gates have been implemented on IBM quantum computer. An efficient one-bit full adder is going to be proposed using the reversible gates like CNOT and TOFFOLI. Later, a 4x4 multiplier will be developed using the proposed one-bit full adder. The proposed multiplier is proved to perform faster calculations compared to the earlier multipliers. The simulation of the presented modules will be done on IBM Quantum computer and the respective probabilities can be observed for different inputs.
In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversible combinational logic circuits with better optimized quantum cost, garbage outputs and delay.The proposed new reversible logic gate is used to design of reversible 1-bit comparator circuit and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR.The proposed new reversible logic gate is represented by quantum implementation.The quantum cost of proposed gate is 4. The quantum cost, garbage output and delay of proposed reversible 1-bit comparator circuit are 6 which is better w. r. t. previously reported results.