Reversible logic has received great attention in last few years as it dissipates very low power. This paper presents the reversible logic synthesis for the n-to-2nfault tolerant decoder, where n is the number of data bits. A low cost 6 × 6 reversible gate is proposed to design a 2-to-4 reversible fault tolerant decoder which has least delay. An algorithm is derived to construct higher bit order decoder. Theoretical explanations certify the novelty of the proposed design. Comparing with previous works, the proposed design shows significant reduction in gate count, quantum cost and delay, which are 66.66%, 8.33%, 16.66%, respectively, with respect to the corresponding metrics of the best existing 2-to-4 fault tolerant decoder. Area and power consumption of the proposed circuit are also estimated.
Reversible logic has received great attention in last few years as it dissipates very low power. This paper presents the reversible logic synthesis for the n-to-2nfault tolerant decoder, where n is the number of data bits. A low cost 6 × 6 reversible gate is proposed to design a 2-to-4 reversible fault tolerant decoder which has least delay. An algorithm is derived to construct higher bit order decoder. Theoretical explanations certify the novelty of the proposed design. Comparing with previous works, the proposed design shows significant reduction in gate count, quantum cost and delay, which are 66.66%, 8.33%, 16.66%, respectively, with respect to the corresponding metrics of the best existing 2-to-4 fault tolerant decoder. Area and power consumption of the proposed circuit are also estimated.
Fault Tolerant reversible decoders are the prerequisite of high performance computing systems.In this paper, an optimized reversible fault tolerant decoder has been proposed by using novel cost effective gates named Reversible Fault Tolerant Decoder (RDC) and Double Fredkin Gate (DFG).Several lower bounds on the numbers of gates, garbage and quantum costs are also proposed to generalize the architecture of n-to-2 n reversible decoder.The comparative performance analysis shows that the proposed design outperforms the existing designs in terms of number of gates used, quantum cost, delay, ancilla inputs and design complexity.
Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.
Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.
Reversible logic circuits have received emerging attentions in recent years. Reversible logic is widely applied in some new technical fields, such as quantum computing, nanocomputing and optical computing and so on. In this paper, three fault tolerant gates are proposed, ZPL gate, ZQC gate and ZC gate. By using the proposed gates, fault tolerant quantum and reversible BCD adder and skip carry BCD adder are designed, which overcome the limitations of the existing methods. The proposed reversible BCD adders have also parity-preserving property. They are better than the existing counterparts, especially in the quantum cost. Proposed designs have been compared with existing designs with respect to the number of gates, number of garbage outputs and quantum cost.
In recent years, research in reversible logic has attracted significance attention leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose Design of Efficient Reversible Binary Comparator. The input circuit and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator are designed using input circuit as first stage and one-bit comparator cell as second stage and so on. The Power consumption, Delay, Garbage outputs and Constant inputs are computed. It is observed that the Quantum cost and Garbage output values are less in the proposed technique compared to the existing approaches.
Today, reversible logic circuits has attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design. In this paper 4 bit reversible comparator based on classical logic circuit is represented which uses existing reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The results show that, the proposed comparator has 4 quantum cost and one constant input less than the prior design. 1