Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

International Journal of Computer Applications

Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis

Md. RiazurRahman

Published Dec 18, 2014• 4 citations
Publisher

Abstract

Fault Tolerant reversible decoders are the prerequisite of high performance computing systems.In this paper, an optimized reversible fault tolerant decoder has been proposed by using novel cost effective gates named Reversible Fault Tolerant Decoder (RDC) and Double Fredkin Gate (DFG).Several lower bounds on the numbers of gates, garbage and quantum costs are also proposed to generalize the architecture of n-to-2 n reversible decoder.The comparative performance analysis shows that the proposed design outperforms the existing designs in terms of number of gates used, quantum cost, delay, ancilla inputs and design complexity.

DOI
10.5120/18881-0160

Related papers

Nanotechnology-Based Efficient Fault Tolerant Decoder in Reversible Logic

Nazma Tara, Md. Kamal Ibne Sufian, Hafiz Md. Hasan Babu

Reversible logic has received great attention in last few years as it dissipates very low power. This paper presents the reversible logic synthesis for the n-to-2nfault tolerant decoder, where n is the number of data bits. A low cost 6 × 6 reversible gate is proposed to design a 2-to-4 reversible fault tolerant decoder which has least delay. An algorithm is derived to construct higher bit order decoder. Theoretical explanations certify the novelty of the proposed design. Comparing with previous works, the proposed design shows significant reduction in gate count, quantum cost and delay, which are 66.66%, 8.33%, 16.66%, respectively, with respect to the corresponding metrics of the best existing 2-to-4 fault tolerant decoder. Area and power consumption of the proposed circuit are also estimated.

IEEE International WIE Conference on Electrical and Computer Engineering•Dec 1, 2017•1 citation

A novel delay & Quantum Cost efficient reversible realization of 2i × j Random Access Memory

Alak Majumder, Prasoon Lata Singh, Nikhil Mishra +2 more

As the conventional irreversible logic dissipates power for losing bits of information, computing engines has to be designed that do not require energy dissipation but only if computation is done logically reversible. Hence, research on reversible logic has been extensively increased now-a-days for its application in Quantum Computing, nanotechnology, QCA and Low power VLSI etc. In this paper, we have realized a Quantum Cost efficient Reversible RAM (RRAM) with a new 3×3 Reversible Gate named Modified Fredkin (MF). While approaching for RRAM we have also proposed a reversible D Flip-flop with minimum quantum cost (QC), a write enabled reversible master slave D Flip-flop & a (i × 2i) reversible decoder which has outperformed the existing designs in terms of quantum cost, ancilla & garbage outputs. We also have analyzed the architectures in terms of logical depth (worst case delay), hardly addressed in available literature.

IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)•Jan 1, 2015•6 citations

Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits

H. V. Jayashree, V K Agarwal, P Venkatasree Charan +1 more

Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in reducing the footprint of the design.

International Conference on Circuits, Control, Communication and Computing (I4C)•Nov 1, 2014•3 citations

Novel designs for fault tolerant reversible binary coded decimal adders

Ri‐Gui Zhou, Yan-Cheng Li, Manqun Zhang

Reversible logic circuits have received emerging attentions in recent years. Reversible logic is widely applied in some new technical fields, such as quantum computing, nanocomputing and optical computing and so on. In this paper, three fault tolerant gates are proposed, ZPL gate, ZQC gate and ZC gate. By using the proposed gates, fault tolerant quantum and reversible BCD adder and skip carry BCD adder are designed, which overcome the limitations of the existing methods. The proposed reversible BCD adders have also parity-preserving property. They are better than the existing counterparts, especially in the quantum cost. Proposed designs have been compared with existing designs with respect to the number of gates, number of garbage outputs and quantum cost.

International Journal of Electronics•Sep 5, 2013•31 citations

In-depth Comparative Analysis of Reversible Gates for Designing Logic Circuits

Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar

Reversible logic is expanding grounds with its applicability to various upcoming technologies and quantum computation. Numerous reversible gates has also been proposed for designing logic circuits apart of basic quantum controlled Toffoli and Fredkin gates. A comparative study and analysis of a range of reversible gates from the literature is presented in this paper to obtain an optimal solution for designing these circuits. The gates are synthesized and implemented to obtain equivalent quantum circuits and operating cost in terms of number of inputs, gate cost, quantum cost, garbage output and ancilla input. The comparison is done at two subsequent levels i.e. gates structural level and circuit design level, providing a better solution for designing logic circuits. It is calculated that, basic gates are 50% efficient at gate level and 33% at design level analysis in terms of gate cost, as compared to the most efficient gates proposed in the literature.

Procedia Computer Science•Jan 1, 2018•36 citations

The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

Heranmoy Maity, Arindam Biswas, Arup K. Bhattacharjee +1 more

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Micro and Nanosystems•Sep 17, 2019•7 citations
Fault Tolerant reversible decoders are the prerequisite of high performance computing systems.In this paper, an optimized reversible fault tolerant decoder has been proposed by using novel cost effective gates named Reversible Fault Tolerant Decoder (RDC) and Double Fredkin Gate (DFG).Several lower bounds on the numbers of gates, garbage and quantum costs are also proposed to generalize the architecture of n-to-2 n reversible decoder.The comparative performance analysis shows that the proposed design outperforms the existing designs in terms of number of gates used, quantum cost, delay, ancilla inputs and design complexity.
Reversible logic has received great attention in last few years as it dissipates very low power. This paper presents the reversible logic synthesis for the n-to-2nfault tolerant decoder, where n is the number of data bits. A low cost 6 × 6 reversible gate is proposed to design a 2-to-4 reversible fault tolerant decoder which has least delay. An algorithm is derived to construct higher bit order decoder. Theoretical explanations certify the novelty of the proposed design. Comparing with previous works, the proposed design shows significant reduction in gate count, quantum cost and delay, which are 66.66%, 8.33%, 16.66%, respectively, with respect to the corresponding metrics of the best existing 2-to-4 fault tolerant decoder. Area and power consumption of the proposed circuit are also estimated.
As the conventional irreversible logic dissipates power for losing bits of information, computing engines has to be designed that do not require energy dissipation but only if computation is done logically reversible. Hence, research on reversible logic has been extensively increased now-a-days for its application in Quantum Computing, nanotechnology, QCA and Low power VLSI etc. In this paper, we have realized a Quantum Cost efficient Reversible RAM (RRAM) with a new 3×3 Reversible Gate named Modified Fredkin (MF). While approaching for RRAM we have also proposed a reversible D Flip-flop with minimum quantum cost (QC), a write enabled reversible master slave D Flip-flop & a (i × 2i) reversible decoder which has outperformed the existing designs in terms of quantum cost, ancilla & garbage outputs. We also have analyzed the architectures in terms of logical depth (worst case delay), hardly addressed in available literature.
Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in reducing the footprint of the design.
Reversible logic circuits have received emerging attentions in recent years. Reversible logic is widely applied in some new technical fields, such as quantum computing, nanocomputing and optical computing and so on. In this paper, three fault tolerant gates are proposed, ZPL gate, ZQC gate and ZC gate. By using the proposed gates, fault tolerant quantum and reversible BCD adder and skip carry BCD adder are designed, which overcome the limitations of the existing methods. The proposed reversible BCD adders have also parity-preserving property. They are better than the existing counterparts, especially in the quantum cost. Proposed designs have been compared with existing designs with respect to the number of gates, number of garbage outputs and quantum cost.
Reversible logic is expanding grounds with its applicability to various upcoming technologies and quantum computation. Numerous reversible gates has also been proposed for designing logic circuits apart of basic quantum controlled Toffoli and Fredkin gates. A comparative study and analysis of a range of reversible gates from the literature is presented in this paper to obtain an optimal solution for designing these circuits. The gates are synthesized and implemented to obtain equivalent quantum circuits and operating cost in terms of number of inputs, gate cost, quantum cost, garbage output and ancilla input. The comparison is done at two subsequent levels i.e. gates structural level and circuit design level, providing a better solution for designing logic circuits. It is calculated that, basic gates are 50% efficient at gate level and 33% at design level analysis in terms of gate cost, as compared to the most efficient gates proposed in the literature.
Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.