IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)

A novel delay & Quantum Cost efficient reversible realization of 2i × j Random Access Memory

Alak Majumder, Prasoon Lata Singh, Nikhil Mishra, Abir Jyoti Mondal, Barnali Chowdhury

Published Jan 1, 2015• 6 citations

Abstract

As the conventional irreversible logic dissipates power for losing bits of information, computing engines has to be designed that do not require energy dissipation but only if computation is done logically reversible. Hence, research on reversible logic has been extensively increased now-a-days for its application in Quantum Computing, nanotechnology, QCA and Low power VLSI etc. In this paper, we have realized a Quantum Cost efficient Reversible RAM (RRAM) with a new 3×3 Reversible Gate named Modified Fredkin (MF). While approaching for RRAM we have also proposed a reversible D Flip-flop with minimum quantum cost (QC), a write enabled reversible master slave D Flip-flop & a (i × 2i) reversible decoder which has outperformed the existing designs in terms of quantum cost, ancilla & garbage outputs. We also have analyzed the architectures in terms of logical depth (worst case delay), hardly addressed in available literature.

DOI: 10.1109/vlsi-sata.2015.7050474

Related papers

Reducing Delay and Quantum Cost in the Novel Design of Reversible Memory Elements

Prasoon Lata Singh, Alak Majumder, Barnali Chowdhury +2 more

In a computational model, that uses transitions from one state of the abstract machine to another, a necessary condition for reversibility is that, the relation of the mapping from states to their successors must be one-to-one. In these works, the primary focus of design is to optimize number of reversible gates and garbage outputs. The calculation of number of gates is not a good option to check the complexity of a circuit as each gate has different architectural complexity decided by a parameter called quantum cost. Delay, hardly addressed in the existing works available in literature, is another good parameter to be optimized for fast reversible computation. In this work, we have presented novel designs of basic sequential circuits like latch that are optimum in terms of delay, quantum cost and garbage. We have also demonstrated quantum cost efficient D-FF, SR-FF, JK-FF & T-FF, along with their master slave configurations.

Procedia Computer ScienceJan 1, 201514 citations

Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis

Md. RiazurRahman

Fault Tolerant reversible decoders are the prerequisite of high performance computing systems.In this paper, an optimized reversible fault tolerant decoder has been proposed by using novel cost effective gates named Reversible Fault Tolerant Decoder (RDC) and Double Fredkin Gate (DFG).Several lower bounds on the numbers of gates, garbage and quantum costs are also proposed to generalize the architecture of n-to-2 n reversible decoder.The comparative performance analysis shows that the proposed design outperforms the existing designs in terms of number of gates used, quantum cost, delay, ancilla inputs and design complexity.

International Journal of Computer ApplicationsDec 18, 20144 citations

Quantum Cost-Efficient Design of Synchronous Reversible Shift Registers using Reversible Logic

Shivangi Gupta, Rahul Kumar, Somesh Kumar

Reversible circuits are one of the most promising technologies for replicating inputs from recorded outputs, and it results in lower power dissipation. All gates such as NAND, AND, OR, NOR etc. are irreversible in nature and consume energy during calculations. Similar to quantum circuits, reversible logic circuitry does not consume energy throughout the calculation cycle. Due to this, reversible circuits can be used for quantum communication and other low-power applications. Registers are one of the most important storage components utilised in a wide range of real-time operations. Using expressions of exclusive-or sum of products (ESOP) and modified Fredkin gates, this work presents a novel way for creating a quantum cost-effective universal register circuit. The designed universal register circuitry for left and right shifts are tested in the Xilinx Vivado simulator to ensure that they are functional and logically correct. The proposed universal registers outperform the standard designs in terms of garbage outputs (GO), quantum cost (QC), gate count (GC), and Ancilla inputs (AI), according to the comparative analysis.

IEEE Bombay Section Signature Conference (IBSSC)Nov 18, 20212 citations

Design of low quantum cost reversible BCD adder

Chua Shin Cheng, Lenin Gopal, Amandeep Singh Sidhu +1 more

Reversible logic is one of the emerging computational methodologies which assures zero power dissipation through theoretical laws of thermodynamics. It has received significant interest in application on quantum computing, nanotechnologies and low power computing devices. In this work, we present a reversible logic implementation for Binary Coded Decimal (BCD) adder which is designed to obtain lowest quantum cost value. Other parameters such as ancilla input, garbage output and delay are kept at minimal. Experiment result shows that the proposed work outperforms other designs in terms of quantum cost. Considering for a 1 digit BCD adder, it has a 4% improvement in terms of quantum cost compared to the current best existing ones. The improvement range increases as the BCD digit becomes larger.

IEEE International Conference on Control System, Computing and EngineeringNov 1, 20150 citations

A Compact Quantum Cost-Efficient Design of a Reversible Binary Counter

Mubin Ul Haque, Zarrin Tasnim Sworna, Sadia Afrin +1 more

One of the important aspects of Very Large Scale Integration (VLSI) is the power dissipation as the number of devices integrated on a single chip increases progressively. In order to overcome the difficulties of high power consumption of a single chip, it is necessary to introduce reversible logic. Reversible logic allows complete reproduction of the inputs from outputs. As there is no bit or information loss, reversible logic leads to zero heat dissipation. The potential applications of reversible logic include Quantum computing, DNA computing, Nanotechnology, Optoelectronics and many more. Counter circuit stores the number of times of occurrence of a particular event based on the clock pulse. An efficient reversible binary up/down counter has been proposed in this paper implementing an efficient algorithm. MSH gate has been used as D-latch, HNG gate and TS3 gate has been used for incremental count. The proposed counter circuit has 31.25% improvement in terms of quantum cost and delay, 58.82% improvement in terms of ancillary input and 5.8% improvement in terms of garbage output compared to existing best known circuits.

IEEE International WIE Conference on Electrical and Computer EngineeringNov 1, 20193 citations

Efficient Approaches for Designing Quantum Costs of Various Reversible Gates

M surekha

Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word.Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design.The principal objective of this work is to argue for quantum implementation of various reversible logic gates by using C-NOT, Controlled-V and Controlled-V + gates.The present work presents parallel adder/subtractor (with over flow detection), as well as Binary coded decimal adder (BCD) in terms of number of gates, garbage outputs, quantum cost, delay and hardware complexity compared to existing design.

International Journal of Engineering StudiesJun 30, 201721 citations