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IEEE Bombay Section Signature Conference (IBSSC)

Quantum Cost-Efficient Design of Synchronous Reversible Shift Registers using Reversible Logic

Shivangi Gupta, Rahul Kumar, Somesh Kumar

Published Nov 18, 2021• 2 citations
Publisher

Abstract

Reversible circuits are one of the most promising technologies for replicating inputs from recorded outputs, and it results in lower power dissipation. All gates such as NAND, AND, OR, NOR etc. are irreversible in nature and consume energy during calculations. Similar to quantum circuits, reversible logic circuitry does not consume energy throughout the calculation cycle. Due to this, reversible circuits can be used for quantum communication and other low-power applications. Registers are one of the most important storage components utilised in a wide range of real-time operations. Using expressions of exclusive-or sum of products (ESOP) and modified Fredkin gates, this work presents a novel way for creating a quantum cost-effective universal register circuit. The designed universal register circuitry for left and right shifts are tested in the Xilinx Vivado simulator to ensure that they are functional and logically correct. The proposed universal registers outperform the standard designs in terms of garbage outputs (GO), quantum cost (QC), gate count (GC), and Ancilla inputs (AI), according to the comparative analysis.

DOI
10.1109/ibssc53889.2021.9673451

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Reversible circuits are one of the most promising technologies for replicating inputs from recorded outputs, and it results in lower power dissipation. All gates such as NAND, AND, OR, NOR etc. are irreversible in nature and consume energy during calculations. Similar to quantum circuits, reversible logic circuitry does not consume energy throughout the calculation cycle. Due to this, reversible circuits can be used for quantum communication and other low-power applications. Registers are one of the most important storage components utilised in a wide range of real-time operations. Using expressions of exclusive-or sum of products (ESOP) and modified Fredkin gates, this work presents a novel way for creating a quantum cost-effective universal register circuit. The designed universal register circuitry for left and right shifts are tested in the Xilinx Vivado simulator to ensure that they are functional and logically correct. The proposed universal registers outperform the standard designs in terms of garbage outputs (GO), quantum cost (QC), gate count (GC), and Ancilla inputs (AI), according to the comparative analysis.
Reversible circuits are one of the most promising technologies that allow the reproduction of the inputs from the observed outputs and thus reducing the power dissipation in the form of heat. Many basic and universal logic gates i.e. nand, nor, or, and etc. are irreversible and result in energy consumption during calculations. In the reversible technology, like quantum circuits energy is not consumed during the entire calculation process and these circuits can be used for low-power and quantum communication applications circuits. Counters are considered as one of the most important sequential circuits used in many real-time applications. This paper presents a new approach to design a quantum cost-effective reversible up/down counter circuit using exclusive-or sum of product (ESOP) expressions and TR gates. The proposed counter circuits are simulated in the Xilinx Vivado simulator to verify the functionality of the proposed designs. The comparative study indicates that the proposed counters are superior to the best previous designs in terms of quantum cost (QC) and gate count (GC). Moreover, they are very close to or better than the previously available designs in terms of garbage outputs (GO) and Ancilla inputs (AI).
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
Reversible logic provides a foundation for nextgeneration computing systems, particularly in quantum and emerging nanotechnology-based architectures. Unlike conventional logic, reversible gates preserve information and support backward computation, making them crucial for designing quantum circuits. This paper introduces a reversible Arithmetic and Logic Unit (ALU) that performs eight fundamental operations-AND, OR, NOT, XOR, addition, subtraction, increment, and decrement-using Fredkin, Peres, TR, and modified Fredkin gates. A dedicated control unit manages operation selection, ensuring functional flexibility and circuit efficiency. The proposed design achieves significant improvements by minimizing ancilla inputs, quantum cost and garbage outputs, resulting in a total quantum cost of 71 and contains 16 reversible gates and 14 garbage outputs. The architecture was modeled and verified using Xilinx Vivado HLS and ISE 14.7, and implemented on the Nexys A7 (Artix-7) FPGA platform. Comparative analysis demonstrates better efficiency than existing reversible ALU designs, establishing the proposed circuit as a strong candidate for quantum computing and other advanced computing paradigms.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
Reversible logic is expanding grounds with its applicability to various upcoming technologies and quantum computation. Numerous reversible gates has also been proposed for designing logic circuits apart of basic quantum controlled Toffoli and Fredkin gates. A comparative study and analysis of a range of reversible gates from the literature is presented in this paper to obtain an optimal solution for designing these circuits. The gates are synthesized and implemented to obtain equivalent quantum circuits and operating cost in terms of number of inputs, gate cost, quantum cost, garbage output and ancilla input. The comparison is done at two subsequent levels i.e. gates structural level and circuit design level, providing a better solution for designing logic circuits. It is calculated that, basic gates are 50% efficient at gate level and 33% at design level analysis in terms of gate cost, as compared to the most efficient gates proposed in the literature.