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Devices for Integrated Circuit (DevIC)

Design of quantum cost efficient 4-bit reversible universal shift register

Heranmoy Maity, Arindam Biswas, Anup Kr. Bhattacherjee, Anita Pal

Published Mar 1, 2017• 9 citations
Publisher

Abstract

This paper proposed the design of quantum cost efficient 4-bit reversible universal shift register(RUSR) using existing reversible logic gates. The proposed design is very useful in quantum computing due to its low quantum cost, less no. of reversible logic gate and low garbage outputs. The quantum cost(QC), garbage output(GO), number of gates are respectively 68, 20 and 16 for proposed work.

DOI
10.1109/devic.2017.8073903

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This paper proposed the design of quantum cost efficient 4-bit reversible universal shift register(RUSR) using existing reversible logic gates. The proposed design is very useful in quantum computing due to its low quantum cost, less no. of reversible logic gate and low garbage outputs. The quantum cost(QC), garbage output(GO), number of gates are respectively 68, 20 and 16 for proposed work.
In this paper, we have proposed the design of quantum cost (QC) optimized 4-bit reversible universal shift register (RUSR) using reduced number of reversible logic gates. The proposed design is very useful in quantum computing due to its low QC, less no. of reversible logic gate and less delay. The QC, no. of gates, garbage outputs (GOs) are respectively 64, 8 and 16 for proposed work. The improvement of proposed work is also presented. The QC is 5.88% to 70.9% improved, no. of gate is 60% to 83.33% improved with compared to latest reported result.
Reversible circuits are one of the most promising technologies for replicating inputs from recorded outputs, and it results in lower power dissipation. All gates such as NAND, AND, OR, NOR etc. are irreversible in nature and consume energy during calculations. Similar to quantum circuits, reversible logic circuitry does not consume energy throughout the calculation cycle. Due to this, reversible circuits can be used for quantum communication and other low-power applications. Registers are one of the most important storage components utilised in a wide range of real-time operations. Using expressions of exclusive-or sum of products (ESOP) and modified Fredkin gates, this work presents a novel way for creating a quantum cost-effective universal register circuit. The designed universal register circuitry for left and right shifts are tested in the Xilinx Vivado simulator to ensure that they are functional and logically correct. The proposed universal registers outperform the standard designs in terms of garbage outputs (GO), quantum cost (QC), gate count (GC), and Ancilla inputs (AI), according to the comparative analysis.
Today, reversible logic circuits has attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design. In this paper 4 bit reversible comparator based on classical logic circuit is represented which uses existing reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The results show that, the proposed comparator has 4 quantum cost and one constant input less than the prior design. 1
Reversible logic gates are critical components in the field of quantum computing and low-power digital circuits, as they allow for the retrieval of input states from output states without any loss of information. This property ensures minimal energy dissipation, aligning with the principles of reversible computation. Their applications extend to quantum computing, cryptographic systems, and error detection and correction mechanisms. This paper presents a novel design for a Reversible D Flip-Flop (RDFF) and a 4-bit Linear Feedback Shift Register (LFSR). The Linear Feedback Shift Register (LFSR) is built utilizing four Register-Driven D Flip-Flops (RDFFs) and a feedback mechanism that incorporates a Feynman Gate. This configuration successfully showcases the capacity to generate pseudo-random sequences. The LFSR design demonstrates a 10% improvement in Total Reversible Logic Implementation Cost and 27% enhancement in quantum cost, making it a more resource-efficient option for reversible computing. This work makes a valuable contribution to the field of reversible computing by offering efficient designs for essential components.
Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.
Reversible logic is one of the emerging technologies having promising applications in quantum computing. In this work, we present new design of the reversible BCD adder that has been primarily optimized for the number of ancilla input bits and the number of garbage outputs. The number of ancilla input bits and the garbage outputs is primarily considered as an optimization criteria as it is extremely difficult to realize a quantum computer with many qubits. As the optimization of ancilla input bits and the garbage outputs may degrade the design in terms of the quantum cost and the delay, thus the quantum cost and the delay parameters are also considered for optimization with primary focus towards the optimization of the number of ancilla input bits and the garbage outputs. Firstly, we propose a new design of the reversible ripple carry adder having the input carry Co and is designed with no ancilla input bits. The proposed reversible ripple carry adder design with no ancilla input bits has less quantum cost and the logic depth (delay) compared to its existing counterparts. The existing reversible Peres gate and a new reversible gate called the TR gate is efficiently utilized to improve the quantum cost and the delay of the reversible ripple carry adder. The improved quantum design of the TR gate is also illustrated. Finally, the reversible design of the BCD adder is presented which is based on a 4 bit reversible binary adder to add the BCD number, and finally the conversion of the binary result to the BCD format using a reversible binary to BCD converter.