One of the important aspects of Very Large Scale Integration (VLSI) is the power dissipation as the number of devices integrated on a single chip increases progressively. In order to overcome the difficulties of high power consumption of a single chip, it is necessary to introduce reversible logic. Reversible logic allows complete reproduction of the inputs from outputs. As there is no bit or information loss, reversible logic leads to zero heat dissipation. The potential applications of reversible logic include Quantum computing, DNA computing, Nanotechnology, Optoelectronics and many more. Counter circuit stores the number of times of occurrence of a particular event based on the clock pulse. An efficient reversible binary up/down counter has been proposed in this paper implementing an efficient algorithm. MSH gate has been used as D-latch, HNG gate and TS3 gate has been used for incremental count. The proposed counter circuit has 31.25% improvement in terms of quantum cost and delay, 58.82% improvement in terms of ancillary input and 5.8% improvement in terms of garbage output compared to existing best known circuits.
One of the important aspects of Very Large Scale Integration (VLSI) is the power dissipation as the number of devices integrated on a single chip increases progressively. In order to overcome the difficulties of high power consumption of a single chip, it is necessary to introduce reversible logic. Reversible logic allows complete reproduction of the inputs from outputs. As there is no bit or information loss, reversible logic leads to zero heat dissipation. The potential applications of reversible logic include Quantum computing, DNA computing, Nanotechnology, Optoelectronics and many more. Counter circuit stores the number of times of occurrence of a particular event based on the clock pulse. An efficient reversible binary up/down counter has been proposed in this paper implementing an efficient algorithm. MSH gate has been used as D-latch, HNG gate and TS3 gate has been used for incremental count. The proposed counter circuit has 31.25% improvement in terms of quantum cost and delay, 58.82% improvement in terms of ancillary input and 5.8% improvement in terms of garbage output compared to existing best known circuits.
Reversible circuits are one of the most promising technologies that allow the reproduction of the inputs from the observed outputs and thus reducing the power dissipation in the form of heat. Many basic and universal logic gates i.e. nand, nor, or, and etc. are irreversible and result in energy consumption during calculations. In the reversible technology, like quantum circuits energy is not consumed during the entire calculation process and these circuits can be used for low-power and quantum communication applications circuits. Counters are considered as one of the most important sequential circuits used in many real-time applications. This paper presents a new approach to design a quantum cost-effective reversible up/down counter circuit using exclusive-or sum of product (ESOP) expressions and TR gates. The proposed counter circuits are simulated in the Xilinx Vivado simulator to verify the functionality of the proposed designs. The comparative study indicates that the proposed counters are superior to the best previous designs in terms of quantum cost (QC) and gate count (GC). Moreover, they are very close to or better than the previously available designs in terms of garbage outputs (GO) and Ancilla inputs (AI).
Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.
Reversible logic is one of the emerging computational methodologies which assures zero power dissipation through theoretical laws of thermodynamics. It has received significant interest in application on quantum computing, nanotechnologies and low power computing devices. In this work, we present a reversible logic implementation for Binary Coded Decimal (BCD) adder which is designed to obtain lowest quantum cost value. Other parameters such as ancilla input, garbage output and delay are kept at minimal. Experiment result shows that the proposed work outperforms other designs in terms of quantum cost. Considering for a 1 digit BCD adder, it has a 4% improvement in terms of quantum cost compared to the current best existing ones. The improvement range increases as the BCD digit becomes larger.
Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit. Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,