Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Journal of Engineering Science and Technology Review

Design of Reversible Combinational Circuits Using New Reversible Logic Gate

1 Dept. of ECE, NSHM Knowledge Campus Durgapur, Durgapur, W.B, India, Heranmoy Maity, Arindam Biswas, Anup Kumar Bhattacharjee, Anita Pal

Published Oct 1, 2018• 6 citations
Publisher

Abstract

In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversible combinational logic circuits with better optimized quantum cost, garbage outputs and delay.The proposed new reversible logic gate is used to design of reversible 1-bit comparator circuit and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR.The proposed new reversible logic gate is represented by quantum implementation.The quantum cost of proposed gate is 4. The quantum cost, garbage output and delay of proposed reversible 1-bit comparator circuit are 6 which is better w. r. t. previously reported results.

DOI
10.25103/jestr.115.21

Related papers

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

Heranmoy Maity, Arijit Kumar Barik, Arindam Biswas +2 more

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Journal of Circuits Systems and Computers•Feb 14, 2018•16 citations

The design of optimal reversible comparator circuit using new quantum gates

A Slimani, Achour Benslama

Abstract This paper presents a novel approach for designing reversible n-bit comparator based on new quantum gates. Their quantum equivalent implementations are also proposed. The design of comparator circuits is completed by using existing reversible gates and the above new reversible circuits. The comparative results are presented in terms of quantum cost, quantum delay and garbage outputs.

Journal of Physics Conference Series•Jan 1, 2021•4 citations

An optimized design of binary comparator circuit in quantum computing

Ankur Sarker, M. Shamiul Amin, Avishek Bose +1 more

Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.

International Conference on Informatics, Electronics & Vision (ICIEV)•May 1, 2014•6 citations

4 Bit Comparator Design Based on Reversible Logic Gates

Soolmaz Abbasalizadeh, Behjat Forouzandeh, Hossein Aghababa

Today, reversible logic circuits has attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design. In this paper 4 bit reversible comparator based on classical logic circuit is represented which uses existing reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The results show that, the proposed comparator has 4 quantum cost and one constant input less than the prior design. 1

Lecture Notes on Information Theory•Jan 1, 2013•9 citations

A new reversible design of BCD adder

Himanshu Thapliyal, Nagarajan Ranganathan

Reversible logic is one of the emerging technologies having promising applications in quantum computing. In this work, we present new design of the reversible BCD adder that has been primarily optimized for the number of ancilla input bits and the number of garbage outputs. The number of ancilla input bits and the garbage outputs is primarily considered as an optimization criteria as it is extremely difficult to realize a quantum computer with many qubits. As the optimization of ancilla input bits and the garbage outputs may degrade the design in terms of the quantum cost and the delay, thus the quantum cost and the delay parameters are also considered for optimization with primary focus towards the optimization of the number of ancilla input bits and the garbage outputs. Firstly, we propose a new design of the reversible ripple carry adder having the input carry Co and is designed with no ancilla input bits. The proposed reversible ripple carry adder design with no ancilla input bits has less quantum cost and the logic depth (delay) compared to its existing counterparts. The existing reversible Peres gate and a new reversible gate called the TR gate is efficiently utilized to improve the quantum cost and the delay of the reversible ripple carry adder. The improved quantum design of the TR gate is also illustrated. Finally, the reversible design of the BCD adder is presented which is based on a 4 bit reversible binary adder to add the BCD number, and finally the conversion of the binary result to the BCD format using a reversible binary to BCD converter.

Design, Automation, and Test in Europe•Mar 1, 2011•66 citations

Design of Efficient Reversible Binary Comparator

H. G. Rangaraju, Vinayak Hegde, K. Raja +1 more

In recent years, research in reversible logic has attracted significance attention leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose Design of Efficient Reversible Binary Comparator. The input circuit and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator are designed using input circuit as first stage and one-bit comparator cell as second stage and so on. The Power consumption, Delay, Garbage outputs and Constant inputs are computed. It is observed that the Quantum cost and Garbage output values are less in the proposed technique compared to the existing approaches.

Procedia Engineering•Jan 1, 2012•20 citations
In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversible combinational logic circuits with better optimized quantum cost, garbage outputs and delay.The proposed new reversible logic gate is used to design of reversible 1-bit comparator circuit and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR.The proposed new reversible logic gate is represented by quantum implementation.The quantum cost of proposed gate is 4. The quantum cost, garbage output and delay of proposed reversible 1-bit comparator circuit are 6 which is better w. r. t. previously reported results.
In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.
Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.
Today, reversible logic circuits has attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design. In this paper 4 bit reversible comparator based on classical logic circuit is represented which uses existing reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The results show that, the proposed comparator has 4 quantum cost and one constant input less than the prior design. 1
Reversible logic is one of the emerging technologies having promising applications in quantum computing. In this work, we present new design of the reversible BCD adder that has been primarily optimized for the number of ancilla input bits and the number of garbage outputs. The number of ancilla input bits and the garbage outputs is primarily considered as an optimization criteria as it is extremely difficult to realize a quantum computer with many qubits. As the optimization of ancilla input bits and the garbage outputs may degrade the design in terms of the quantum cost and the delay, thus the quantum cost and the delay parameters are also considered for optimization with primary focus towards the optimization of the number of ancilla input bits and the garbage outputs. Firstly, we propose a new design of the reversible ripple carry adder having the input carry Co and is designed with no ancilla input bits. The proposed reversible ripple carry adder design with no ancilla input bits has less quantum cost and the logic depth (delay) compared to its existing counterparts. The existing reversible Peres gate and a new reversible gate called the TR gate is efficiently utilized to improve the quantum cost and the delay of the reversible ripple carry adder. The improved quantum design of the TR gate is also illustrated. Finally, the reversible design of the BCD adder is presented which is based on a 4 bit reversible binary adder to add the BCD number, and finally the conversion of the binary result to the BCD format using a reversible binary to BCD converter.
In recent years, research in reversible logic has attracted significance attention leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose Design of Efficient Reversible Binary Comparator. The input circuit and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator are designed using input circuit as first stage and one-bit comparator cell as second stage and so on. The Power consumption, Delay, Garbage outputs and Constant inputs are computed. It is observed that the Quantum cost and Garbage output values are less in the proposed technique compared to the existing approaches.