Multi-valued quantum logic presents significant advantages over conventional binary logic, including enhanced information processing capacity and reduced circuit complexity. As a fundamental component of quantum arithmetic units, the efficiency of multi-valued quantum adders is critical to overall system performance. In this paper, a universal construction scheme for multi-valued quantum half adders, full adders, and parallel adders is introduced based on 1-qudit gates and Muthukrishnan–Stroud gates. The proposed design optimizes the carry propagation mechanism from a one-to-one to a one-to-many architecture, thereby reducing the quantum gate count. A key advantage of this approach is the linear scaling of quantum gate size with the system dimension d. The constructed d-valued quantum adder maintains an optimal number of constant inputs and garbage outputs. For dimensions [Formula: see text], the proposed design demonstrates significant improvements in quantum cost and hardware complexity compared to existing methods.
Multi-valued quantum logic presents significant advantages over conventional binary logic, including enhanced information processing capacity and reduced circuit complexity. As a fundamental component of quantum arithmetic units, the efficiency of multi-valued quantum adders is critical to overall system performance. In this paper, a universal construction scheme for multi-valued quantum half adders, full adders, and parallel adders is introduced based on 1-qudit gates and Muthukrishnan–Stroud gates. The proposed design optimizes the carry propagation mechanism from a one-to-one to a one-to-many architecture, thereby reducing the quantum gate count. A key advantage of this approach is the linear scaling of quantum gate size with the system dimension d. The constructed d-valued quantum adder maintains an optimal number of constant inputs and garbage outputs. For dimensions [Formula: see text], the proposed design demonstrates significant improvements in quantum cost and hardware complexity compared to existing methods.
Abstract Multi-valued quantum adder circuits, based on multi-valued logic, are significant components in numerous quantum algorithms. Their low-cost implementations can enhance the efficiency of these algorithms. In this paper, innovative universal architectures for d(d>3)-level quantum half-adder, full-adder, parallel adder, and parallel adder/subtractor circuits are designed using d-level 1-qudit (quantum digit) and M–S gates. To demonstrate the effectiveness of these architectures, quaternary adder circuits derived from them are displayed and compared with several existing counterparts. Judging by the results, these circuits exhibit reductions in quantum cost (QC), hardware complexity (HC), number of constant inputs (NCIs), and number of garbage outputs (NGOs).
Abstract Multi-valued quantum logic circuits possess the ability to store and process more intricate information than binary quantum logic circuits. A key component within numerous intricate computational circuits is the multi-valued quantum adder circuit. The primary objective of this paper is to propose a multi-valued quantum full adder and an optimal replacement of two multi-valued Toffoli gate cascades which can effectively reduce the quantum cost of the circuit. Constructed from multi-valued 1-qudit and 2-qudit M-S gates, this adder circuit is designed by effectively setting the control conditions of multi-valued quantum Toffoli gates. For a quaternary quantum adder based on this M-S gate architecture, the number of QC, 1-qudit gates, and 2-qudit gates are 48.6%, 46.2%, and 54.2%, respectively, of the previous design. Additionally, NCI and NGO are consistent with prior adder. It shows the potential applications of complex quantum reversible logic circuits.
Abstract Multi-valued quantum systems have more significant advantages in computational performance than binary quantum system, since the circuit design is more compact and efficient in multi-valued quantum systems. Hence, synthesizing multi-valued logic circuits is a better choice for future quantum computing technology. A subcircuit in the Grover’s algorithm is called an oracle, which inputs a set of quantum qudits and gives an output according to the search conditions. Greater-than/less-than/equality comparators are widely used in search conditions. In this paper, the ternary Toffoli gate proposed by Monfared and Haghparast is extended to multi-valued under certain conditions, and the existing optimal quaternary n-qudit comparator is optimized using the multi-valued Toffoli gate. In addition, we design universal multi-valued equality/greater-than/less-than comparators and complementary component, which constitute a comprehensive multi-valued n-qudit comparator. Compared to existing comparator circuits, these comparator circuits are more efficient in terms of quantum cost, garbage output, hardware complexity, and constant input.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
The ternary quantum circuit is very useful in arithmetic and logic operations. This circuit has several advantages as it reduces power dissipation, step time, etc. Adder circuit is the main block of various computing units and for several other complex computer designs. In this current paper, we have used generalized ternary gate (GTG) and reversible gates for the synthesis of reversible half adder and a full adder circuits. The presented designs offer reduced constant inputs and less quantum cost, compared to existing designs. Our proposed design allows a reduction of 40% of the cost and 25% of the number of gates used.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.