Abstract Multi-valued quantum systems have more significant advantages in computational performance than binary quantum system, since the circuit design is more compact and efficient in multi-valued quantum systems. Hence, synthesizing multi-valued logic circuits is a better choice for future quantum computing technology. A subcircuit in the Grover’s algorithm is called an oracle, which inputs a set of quantum qudits and gives an output according to the search conditions. Greater-than/less-than/equality comparators are widely used in search conditions. In this paper, the ternary Toffoli gate proposed by Monfared and Haghparast is extended to multi-valued under certain conditions, and the existing optimal quaternary n-qudit comparator is optimized using the multi-valued Toffoli gate. In addition, we design universal multi-valued equality/greater-than/less-than comparators and complementary component, which constitute a comprehensive multi-valued n-qudit comparator. Compared to existing comparator circuits, these comparator circuits are more efficient in terms of quantum cost, garbage output, hardware complexity, and constant input.
Abstract Multi-valued quantum systems have more significant advantages in computational performance than binary quantum system, since the circuit design is more compact and efficient in multi-valued quantum systems. Hence, synthesizing multi-valued logic circuits is a better choice for future quantum computing technology. A subcircuit in the Grover’s algorithm is called an oracle, which inputs a set of quantum qudits and gives an output according to the search conditions. Greater-than/less-than/equality comparators are widely used in search conditions. In this paper, the ternary Toffoli gate proposed by Monfared and Haghparast is extended to multi-valued under certain conditions, and the existing optimal quaternary n-qudit comparator is optimized using the multi-valued Toffoli gate. In addition, we design universal multi-valued equality/greater-than/less-than comparators and complementary component, which constitute a comprehensive multi-valued n-qudit comparator. Compared to existing comparator circuits, these comparator circuits are more efficient in terms of quantum cost, garbage output, hardware complexity, and constant input.
Abstract Multi-valued quantum logic circuits possess the ability to store and process more intricate information than binary quantum logic circuits. A key component within numerous intricate computational circuits is the multi-valued quantum adder circuit. The primary objective of this paper is to propose a multi-valued quantum full adder and an optimal replacement of two multi-valued Toffoli gate cascades which can effectively reduce the quantum cost of the circuit. Constructed from multi-valued 1-qudit and 2-qudit M-S gates, this adder circuit is designed by effectively setting the control conditions of multi-valued quantum Toffoli gates. For a quaternary quantum adder based on this M-S gate architecture, the number of QC, 1-qudit gates, and 2-qudit gates are 48.6%, 46.2%, and 54.2%, respectively, of the previous design. Additionally, NCI and NGO are consistent with prior adder. It shows the potential applications of complex quantum reversible logic circuits.
Multi-valued quantum logic presents significant advantages over conventional binary logic, including enhanced information processing capacity and reduced circuit complexity. As a fundamental component of quantum arithmetic units, the efficiency of multi-valued quantum adders is critical to overall system performance. In this paper, a universal construction scheme for multi-valued quantum half adders, full adders, and parallel adders is introduced based on 1-qudit gates and Muthukrishnan–Stroud gates. The proposed design optimizes the carry propagation mechanism from a one-to-one to a one-to-many architecture, thereby reducing the quantum gate count. A key advantage of this approach is the linear scaling of quantum gate size with the system dimension d. The constructed d-valued quantum adder maintains an optimal number of constant inputs and garbage outputs. For dimensions [Formula: see text], the proposed design demonstrates significant improvements in quantum cost and hardware complexity compared to existing methods.
Abstract Multi-valued quantum adder circuits, based on multi-valued logic, are significant components in numerous quantum algorithms. Their low-cost implementations can enhance the efficiency of these algorithms. In this paper, innovative universal architectures for d(d>3)-level quantum half-adder, full-adder, parallel adder, and parallel adder/subtractor circuits are designed using d-level 1-qudit (quantum digit) and M–S gates. To demonstrate the effectiveness of these architectures, quaternary adder circuits derived from them are displayed and compared with several existing counterparts. Judging by the results, these circuits exhibit reductions in quantum cost (QC), hardware complexity (HC), number of constant inputs (NCIs), and number of garbage outputs (NGOs).
Abstract In recent years, quantum computing has emerged as a leading approach for accelerating complex computations, leveraging quantum parallelism and entanglement to surpass classical limits. Although numerous quantum circuits based on reversible gates have been proposed, optimizing circuit efficiency remains a critical challenge, particularly in the noisy intermediate-scale quantum era, where error rates and coherence times constrain performance. Ternary quantum computing, which operates on three-level quantum systems (qutrits), offers a promising alternative by reducing circuit complexity and resource overhead. In particular, balanced ternary logic presents advantages over conventional ternary logic by enhancing resource efficiency and potentially mitigating quantum gate error rates. This paper focuses on two key objectives: first, the synthesis of a reversible 1-qutrit comparator circuit using balanced ternary logic, and second, the extension to a generalized n-qutrit comparator. The proposed 1-qutrit comparator achieves notable improvements over existing unbalanced designs, demonstrating a 65% reduction in quantum cost, 50% fewer constant inputs, and a 33% decrease in garbage outputs. These results highlight the potential of balanced ternary logic to enhance the efficiency of quantum circuits, making it a valuable contribution to the development of scalable and error-resilient quantum hardware.
Reversible logic is fundamental to quantum circuit design, as quantum operations are inherently information-preserving and reversible. While most quantum synthesis methods rely on binary logic, quaternary reversible computing can increase data density, reduce circuit width, and potentially lead to more efficient realizations. We introduce a genetic-algorithm-based approach for designing compact quaternary reversible comparator circuits, which are important components in quantum architectures. This technique utilizes a gate library based on extended Shift and Muthukrishnan–Stroud gates tailored to quaternary systems. Chromosomes encode sequences of quaternary gates, and evolutionary operators search for configurations with minimal quantum cost. Although demonstrated on comparator circuits, the approach applies to any quaternary reversible circuit defined by its truth table. The synthesis process occurs in two phases: candidate circuits first evolve toward correct behavior; then correct circuits are optimized to obtain compact implementations. We evaluate the approach on comparators performing lower-than, greater-than, and equality operations, as well as on a 1-qudit full comparator. The method achieves average quantum cost improvements of about 30% for restoring and 58% for non-restoring configurations compared to existing designs. These reductions support more efficient and more error-resilient quantum circuits, showing that this approach is a strong candidate for quaternary quantum systems.
This paper introduces a new logic structure for reversible quantum circuit synthesis. Our synthesis method aims to minimize the quantum cost of reversible quantum circuits with decoders. In this method, multi-valued input, binary output (MVI) functions are utilized as a mathematical concept only, but the circuits are binary. We introduce the new concept of ``Multi-Valued Input Fixed Polarity Reed-Muller (MVI-RM)" forms. Our decoder-based circuit uses three logical levels in contrast to commonly-used methods based on Exclusive-or Sum of Products (ESOP) with two levels (AND-XOR expressions), realized by Toffoli gates. In general, the high number of input qubits in the resulting Toffoli gates is a problem that greatly impacts the quantum cost. Using decoders decreases the number of input qubits in these Toffoli gates. We present two practical algorithms for three-level circuit synthesis by finding the MVI-FPRM: products-matching and the newly developed butterfly diagrams. The best MVI-FPRM forms are factorized and reduced to approximate Multi-Valued Input Generalized Reed-Muller (MVI-GRM) forms.