Abstract Multi-valued quantum logic circuits possess the ability to store and process more intricate information than binary quantum logic circuits. A key component within numerous intricate computational circuits is the multi-valued quantum adder circuit. The primary objective of this paper is to propose a multi-valued quantum full adder and an optimal replacement of two multi-valued Toffoli gate cascades which can effectively reduce the quantum cost of the circuit. Constructed from multi-valued 1-qudit and 2-qudit M-S gates, this adder circuit is designed by effectively setting the control conditions of multi-valued quantum Toffoli gates. For a quaternary quantum adder based on this M-S gate architecture, the number of QC, 1-qudit gates, and 2-qudit gates are 48.6%, 46.2%, and 54.2%, respectively, of the previous design. Additionally, NCI and NGO are consistent with prior adder. It shows the potential applications of complex quantum reversible logic circuits.
Abstract Multi-valued quantum logic circuits possess the ability to store and process more intricate information than binary quantum logic circuits. A key component within numerous intricate computational circuits is the multi-valued quantum adder circuit. The primary objective of this paper is to propose a multi-valued quantum full adder and an optimal replacement of two multi-valued Toffoli gate cascades which can effectively reduce the quantum cost of the circuit. Constructed from multi-valued 1-qudit and 2-qudit M-S gates, this adder circuit is designed by effectively setting the control conditions of multi-valued quantum Toffoli gates. For a quaternary quantum adder based on this M-S gate architecture, the number of QC, 1-qudit gates, and 2-qudit gates are 48.6%, 46.2%, and 54.2%, respectively, of the previous design. Additionally, NCI and NGO are consistent with prior adder. It shows the potential applications of complex quantum reversible logic circuits.
Multi-valued quantum logic presents significant advantages over conventional binary logic, including enhanced information processing capacity and reduced circuit complexity. As a fundamental component of quantum arithmetic units, the efficiency of multi-valued quantum adders is critical to overall system performance. In this paper, a universal construction scheme for multi-valued quantum half adders, full adders, and parallel adders is introduced based on 1-qudit gates and Muthukrishnan–Stroud gates. The proposed design optimizes the carry propagation mechanism from a one-to-one to a one-to-many architecture, thereby reducing the quantum gate count. A key advantage of this approach is the linear scaling of quantum gate size with the system dimension d. The constructed d-valued quantum adder maintains an optimal number of constant inputs and garbage outputs. For dimensions [Formula: see text], the proposed design demonstrates significant improvements in quantum cost and hardware complexity compared to existing methods.
Abstract Multi-valued quantum adder circuits, based on multi-valued logic, are significant components in numerous quantum algorithms. Their low-cost implementations can enhance the efficiency of these algorithms. In this paper, innovative universal architectures for d(d>3)-level quantum half-adder, full-adder, parallel adder, and parallel adder/subtractor circuits are designed using d-level 1-qudit (quantum digit) and M–S gates. To demonstrate the effectiveness of these architectures, quaternary adder circuits derived from them are displayed and compared with several existing counterparts. Judging by the results, these circuits exhibit reductions in quantum cost (QC), hardware complexity (HC), number of constant inputs (NCIs), and number of garbage outputs (NGOs).
Abstract Multi-valued quantum systems have more significant advantages in computational performance than binary quantum system, since the circuit design is more compact and efficient in multi-valued quantum systems. Hence, synthesizing multi-valued logic circuits is a better choice for future quantum computing technology. A subcircuit in the Grover’s algorithm is called an oracle, which inputs a set of quantum qudits and gives an output according to the search conditions. Greater-than/less-than/equality comparators are widely used in search conditions. In this paper, the ternary Toffoli gate proposed by Monfared and Haghparast is extended to multi-valued under certain conditions, and the existing optimal quaternary n-qudit comparator is optimized using the multi-valued Toffoli gate. In addition, we design universal multi-valued equality/greater-than/less-than comparators and complementary component, which constitute a comprehensive multi-valued n-qudit comparator. Compared to existing comparator circuits, these comparator circuits are more efficient in terms of quantum cost, garbage output, hardware complexity, and constant input.
Efficient arithmetic operations are a prerequisite for practical quantum computing. Optimization efforts focus on two primary metrics: Quantum Cost (QC), determined by the number of non-linear gates, and Logical Depth, which defines the execution speed. Existing literature identifies the HNG gate as the standard for Input-Preserving Reversible Full Adders. HNG gate typically requires a QC of 12 and a logical depth of 5, in the area of classical reversible circuits. This paper proposes the PPKN Gate, a novel design that achieves the same inputpreserving functionality using only one Toffoli gate and five CNOT gates. With a Quantum Cost of 10 and a reduced logical depth of 4, the PPKN gate outperforms the standard HNG gate in both complexity and speed. Furthermore, we present a modular architecture for constructing an n-bit Ripple Carry Adder by cascading PPKN modules.
The minimization of Quantum Cost (QC), specifically the number of Toffoli gates, is a primary objective in the synthesis of reversible arithmetic circuits. For decades, the Peres Full Adder has been considered the benchmark for minimal realizations, requiring 2 Toffoli gates and a Quantum Cost of 12. In this note, we propose a novel reversible Full Adder circuit that utilizes only one Toffoli gate and four CNOT gates. The proposed design achieves a Quantum Cost of 9, representing a 25% reduction compared to the Peres structure, while maintaining a competitive logical depth of 4. We rigorously verify the logic and demonstrate that the reduction is achieved through the automated synthesis framework recently proposed by the authors.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.