Efficient arithmetic operations are a prerequisite for practical quantum computing. Optimization efforts focus on two primary metrics: Quantum Cost (QC), determined by the number of non-linear gates, and Logical Depth, which defines the execution speed. Existing literature identifies the HNG gate as the standard for Input-Preserving Reversible Full Adders. HNG gate typically requires a QC of 12 and a logical depth of 5, in the area of classical reversible circuits. This paper proposes the PPKN Gate, a novel design that achieves the same inputpreserving functionality using only one Toffoli gate and five CNOT gates. With a Quantum Cost of 10 and a reduced logical depth of 4, the PPKN gate outperforms the standard HNG gate in both complexity and speed. Furthermore, we present a modular architecture for constructing an n-bit Ripple Carry Adder by cascading PPKN modules.
Efficient arithmetic operations are a prerequisite for practical quantum computing. Optimization efforts focus on two primary metrics: Quantum Cost (QC), determined by the number of non-linear gates, and Logical Depth, which defines the execution speed. Existing literature identifies the HNG gate as the standard for Input-Preserving Reversible Full Adders. HNG gate typically requires a QC of 12 and a logical depth of 5, in the area of classical reversible circuits. This paper proposes the PPKN Gate, a novel design that achieves the same inputpreserving functionality using only one Toffoli gate and five CNOT gates. With a Quantum Cost of 10 and a reduced logical depth of 4, the PPKN gate outperforms the standard HNG gate in both complexity and speed. Furthermore, we present a modular architecture for constructing an n-bit Ripple Carry Adder by cascading PPKN modules.
The minimization of Quantum Cost (QC), specifically the number of Toffoli gates, is a primary objective in the synthesis of reversible arithmetic circuits. For decades, the Peres Full Adder has been considered the benchmark for minimal realizations, requiring 2 Toffoli gates and a Quantum Cost of 12. In this note, we propose a novel reversible Full Adder circuit that utilizes only one Toffoli gate and four CNOT gates. The proposed design achieves a Quantum Cost of 9, representing a 25% reduction compared to the Peres structure, while maintaining a competitive logical depth of 4. We rigorously verify the logic and demonstrate that the reduction is achieved through the automated synthesis framework recently proposed by the authors.
Abstract Multi-valued quantum logic circuits possess the ability to store and process more intricate information than binary quantum logic circuits. A key component within numerous intricate computational circuits is the multi-valued quantum adder circuit. The primary objective of this paper is to propose a multi-valued quantum full adder and an optimal replacement of two multi-valued Toffoli gate cascades which can effectively reduce the quantum cost of the circuit. Constructed from multi-valued 1-qudit and 2-qudit M-S gates, this adder circuit is designed by effectively setting the control conditions of multi-valued quantum Toffoli gates. For a quaternary quantum adder based on this M-S gate architecture, the number of QC, 1-qudit gates, and 2-qudit gates are 48.6%, 46.2%, and 54.2%, respectively, of the previous design. Additionally, NCI and NGO are consistent with prior adder. It shows the potential applications of complex quantum reversible logic circuits.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently perform BCD addition and implement the required correction logic while maintaining full reversibility. Evaluation results indicate that the proposed designs surpass existing reversible BCD adders, achieving best-case average improvements of 85.12% in delay and 30.75% in quantum cost. These advancements demonstrate the potential of the proposed adders for integration into future quantum-based arithmetic units and scalable reversible computing systems. Moreover, analysis of real banking transaction data underscores the practical importance of BCD addition and its widespread use in accurate and efficient monetary computations.
Abstract Quantum computing (QC) is suitable for reversible computing due to its inherent parallel processing ability and fast speed. It also helps to address the issue of high-power dissipation in classical computing. Moreover, QC gates are the sequence of elementary operations such as single-qubit rotation and two-qubit entanglement. Elementary quantum operations are required to be reduced for the realization of complex computing. In this paper, optimization of 1-Toffoli gate-based quantum full adders (QFAs) in terms of the number of elementary operations with the help of quantum library {Ry, Rz, SWAP SWAP } is carried out. Moreover, the performance of two different 1-Toffoli QFAs is investigated in terms of execution time, fidelity, and number of electrons required to realize the QFAs. Improvement in fidelity is 0.7% and 0.57% for QFA1 and QFA2, respectively, compared to the fidelity of 2-Toffoli QFA. A 9.97% increase in execution time is mandatory for the QFA2 compared to QFA1. The QFA2 takes 5% more number of electrons in comparison to QFA1.
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Next, a novel 3*3 programmable UPG gate capable of calculating the fundamental logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, nbit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, 4*4 reversible gate is presented and verified which is capable of producing the calculations necessary for two-bit comparisons. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. Then, two novel 4*4 reversible logic gates (MRG and PAOG) are proposed with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. A 5*5 structure (MG) is proposed that extends the capabilities of both the MRG and PAOG. The comparator designs are verified and its advantages to previous designs are discussed. Then, reversible implementations of ripple-carry, carry-select and Kogge-Stone carry look-ahead adders are analyzed and compared. Next, implementations of the Kogge-Stone adder with sparsity-4, 8 and 16 were designed, verified and compared. The enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders was selected as the best design, and its implemented in the design of a 32-bit arithmetic logic unit is demonstrated. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed.