Circuit design with no energy dissipation is possible in the reversible logic. Also, using the quantum multiple‐valued logic in the design of circuits due to the reduction of circuit width leads to the smaller chip area and lower power consumption. Quaternary reversible logic potentially has several advantages in comparison to the equivalent ternary and binary quantum technologies. Hence, the quaternary quantum technology is a promising choice for the future digital system design. Here, the authors proposed an efficient design of 1‐qudit and n ‐qudit quantum comparators. The comparator module is widely used in search conditions, such as Grover's quantum search algorithm in quantum computing. The proposed circuits were better than their existing counterparts in terms of quantum cost, the number of constant inputs, the number of garbage outputs, and hardware complexity. To design these circuits, they have used 1‐qudit gates and 2‐qudit Muthukrishnan–Stroud gates. The efficiency of their proposed circuits was reported.
Circuit design with no energy dissipation is possible in the reversible logic. Also, using the quantum multiple‐valued logic in the design of circuits due to the reduction of circuit width leads to the smaller chip area and lower power consumption. Quaternary reversible logic potentially has several advantages in comparison to the equivalent ternary and binary quantum technologies. Hence, the quaternary quantum technology is a promising choice for the future digital system design. Here, the authors proposed an efficient design of 1‐qudit and n ‐qudit quantum comparators. The comparator module is widely used in search conditions, such as Grover's quantum search algorithm in quantum computing. The proposed circuits were better than their existing counterparts in terms of quantum cost, the number of constant inputs, the number of garbage outputs, and hardware complexity. To design these circuits, they have used 1‐qudit gates and 2‐qudit Muthukrishnan–Stroud gates. The efficiency of their proposed circuits was reported.
Abstract Multi-valued quantum systems have more significant advantages in computational performance than binary quantum system, since the circuit design is more compact and efficient in multi-valued quantum systems. Hence, synthesizing multi-valued logic circuits is a better choice for future quantum computing technology. A subcircuit in the Grover’s algorithm is called an oracle, which inputs a set of quantum qudits and gives an output according to the search conditions. Greater-than/less-than/equality comparators are widely used in search conditions. In this paper, the ternary Toffoli gate proposed by Monfared and Haghparast is extended to multi-valued under certain conditions, and the existing optimal quaternary n-qudit comparator is optimized using the multi-valued Toffoli gate. In addition, we design universal multi-valued equality/greater-than/less-than comparators and complementary component, which constitute a comprehensive multi-valued n-qudit comparator. Compared to existing comparator circuits, these comparator circuits are more efficient in terms of quantum cost, garbage output, hardware complexity, and constant input.
Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible4×1multiplexer and1×4demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversiblen×1multiplexer and1×ndemultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.
One of the major problems in designing highly compact digital systems is the rate of power consumption and internal heat generated by the loss of information during the computation. The tendency of current circuit design technologies is towards Nanoscale. Quaternary reversible logic is an emerging technology for the future designing of the quantum systems since quantum reversible circuits can be realized in Nanoscales. The adder building block is an essential part of any computer system. This block must be designed efficiently. We proposed a new quaternary quantum reversible half adder with the quantum cost of 17 and a quaternary quantum reversible full adder with a quantum cost of 23. For the first time in the literature, we report that we proposed quaternary quantum reversible half adder as well as full adder with an optimum number of constant inputs. As the circuit lines in the domain of quantum computation are considered to be a very limited resource, the achievements in this paper are promising. The proposed circuits are efficient in terms of all figures of merits in comparison to the existing counterparts. To design these adder circuits, we used 1-qudit and 2-qudit quaternary gates.
Reversible logic is fundamental to quantum circuit design, as quantum operations are inherently information-preserving and reversible. While most quantum synthesis methods rely on binary logic, quaternary reversible computing can increase data density, reduce circuit width, and potentially lead to more efficient realizations. We introduce a genetic-algorithm-based approach for designing compact quaternary reversible comparator circuits, which are important components in quantum architectures. This technique utilizes a gate library based on extended Shift and Muthukrishnan–Stroud gates tailored to quaternary systems. Chromosomes encode sequences of quaternary gates, and evolutionary operators search for configurations with minimal quantum cost. Although demonstrated on comparator circuits, the approach applies to any quaternary reversible circuit defined by its truth table. The synthesis process occurs in two phases: candidate circuits first evolve toward correct behavior; then correct circuits are optimized to obtain compact implementations. We evaluate the approach on comparators performing lower-than, greater-than, and equality operations, as well as on a 1-qudit full comparator. The method achieves average quantum cost improvements of about 30% for restoring and 58% for non-restoring configurations compared to existing designs. These reductions support more efficient and more error-resilient quantum circuits, showing that this approach is a strong candidate for quaternary quantum systems.
Abstract In recent years, quantum computing has emerged as a leading approach for accelerating complex computations, leveraging quantum parallelism and entanglement to surpass classical limits. Although numerous quantum circuits based on reversible gates have been proposed, optimizing circuit efficiency remains a critical challenge, particularly in the noisy intermediate-scale quantum era, where error rates and coherence times constrain performance. Ternary quantum computing, which operates on three-level quantum systems (qutrits), offers a promising alternative by reducing circuit complexity and resource overhead. In particular, balanced ternary logic presents advantages over conventional ternary logic by enhancing resource efficiency and potentially mitigating quantum gate error rates. This paper focuses on two key objectives: first, the synthesis of a reversible 1-qutrit comparator circuit using balanced ternary logic, and second, the extension to a generalized n-qutrit comparator. The proposed 1-qutrit comparator achieves notable improvements over existing unbalanced designs, demonstrating a 65% reduction in quantum cost, 50% fewer constant inputs, and a 33% decrease in garbage outputs. These results highlight the potential of balanced ternary logic to enhance the efficiency of quantum circuits, making it a valuable contribution to the development of scalable and error-resilient quantum hardware.
Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.