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IEEE Access

Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer

Asma Taheri Monfared, Valentina Ciriani, Tommi Mikkonen, Majid Haghparast

Published Jan 1, 2023• 16 citations
Publisher

Abstract

Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible$4\times 1$multiplexer and$1\times 4$demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversible$n\times 1$multiplexer and$1\times n$demultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.

DOI
10.1109/access.2023.3274118

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Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible4×14\times 14×1multiplexer and1×41\times 41×4demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversiblen×1n\times 1n×1multiplexer and1×n1\times n1×ndemultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.
Abstract In recent years, ternary reversible logic has become a promising paradigm for advancing low-power, high-performance quantum digital systems that preserve information and are energy efficient. This paper focuses on two primary objectives: first, the efficient realization of ternary reversible 3×13 \times 13×1 3 × 1 multiplexers and 1×31 \times 31×3 1 × 3 demultiplexers using quantum gates, specifically 1-qutrit Shift and 3-qutrit Controlled Feynman gates, and second, the design of generalized n×1n \times 1n×1 n × 1 multiplexers and 1×n1 \times n1×n 1 × n demultiplexers. The proposed 9×19 \times 19×1 9 × 1 multiplexer we propose in this study has demonstrated notable improvements in terms of quantum cost (20%), depth (18%), number of constant inputs (60%), and garbage outputs (30%), while the proposed 1×91 \times 91×9 1 × 9 demultiplexer shows a 20% reduction in quantum cost, a 18% reduction in depth, a 33% reduction in constant inputs, and a 50% reduction in garbage outputs, compared to the most efficient existing designs. These optimizations represent an important step forward in the development of more efficient ternary and quantum reversible logic circuits, advancing the scalability of quantum systems.
Reversible computing has emerged as a promising solution for reducing energy dissipation in digital systems by addressing the fundamental limitations caused by information loss.Quaternary reversible logic, which uses multi-valued representations, provides higher information density, reduced interconnect complexity, and better scalability when compared to conventional binary logic.This work presents the design and implementation of a quaternary reversible Arithmetic Logic Unit (ALU) that integrates essential computational modules, including arithmetic units, logical units, memory units, decoders, and multiplexers.The proposed architecture supports efficient data routing and precise operation control through a scalable control unit and a selection-line-based design approach.The designed ALU demonstrates reduced quantum cost, fewer garbage outputs, and minimized constant inputs in comparison with existing reversible ALU designs, while remaining compatible with larger reversible and quantum computing architectures.Simulation results and comparative analysis validate the improved efficiency and low-power potential of the proposed system, making it suitable for next-generation computing applications.The complete design is implemented using Verilog HDL and synthesized and simulated using Xilinx Vivado Design Suite 2025.
Circuit design with no energy dissipation is possible in the reversible logic. Also, using the quantum multiple‐valued logic in the design of circuits due to the reduction of circuit width leads to the smaller chip area and lower power consumption. Quaternary reversible logic potentially has several advantages in comparison to the equivalent ternary and binary quantum technologies. Hence, the quaternary quantum technology is a promising choice for the future digital system design. Here, the authors proposed an efficient design of 1‐qudit and n ‐qudit quantum comparators. The comparator module is widely used in search conditions, such as Grover's quantum search algorithm in quantum computing. The proposed circuits were better than their existing counterparts in terms of quantum cost, the number of constant inputs, the number of garbage outputs, and hardware complexity. To design these circuits, they have used 1‐qudit gates and 2‐qudit Muthukrishnan–Stroud gates. The efficiency of their proposed circuits was reported.
One of the major problems in designing highly compact digital systems is the rate of power consumption and internal heat generated by the loss of information during the computation. The tendency of current circuit design technologies is towards Nanoscale. Quaternary reversible logic is an emerging technology for the future designing of the quantum systems since quantum reversible circuits can be realized in Nanoscales. The adder building block is an essential part of any computer system. This block must be designed efficiently. We proposed a new quaternary quantum reversible half adder with the quantum cost of 17 and a quaternary quantum reversible full adder with a quantum cost of 23. For the first time in the literature, we report that we proposed quaternary quantum reversible half adder as well as full adder with an optimum number of constant inputs. As the circuit lines in the domain of quantum computation are considered to be a very limited resource, the achievements in this paper are promising. The proposed circuits are efficient in terms of all figures of merits in comparison to the existing counterparts. To design these adder circuits, we used 1-qudit and 2-qudit quaternary gates.
Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.
Multiplexer and demultiplexer circuits are among the main circuits in designing the complicated hardware. Therefore, enhancing their performance is very important. In the last few years one of the cases that got the attention of the researchers is designing circuits with low power. Using the reversible logic in designing the circuits can reduce power dissipation and power consumption. Using the ternary logic also leads to a better performance, reducing the power consumption and enhancing of fault tolerance in reversible circuits. In this paper, we have presented quantum reversible ternary multiplexer and demultiplexer circuits, we have used reversible ternary shift and controlled Feynman gates. Presented circuits in this paper have a better performance in compared to the previous designs. The improvements are reported.