Quaternary logic is very suitable for encoded realization of binary logic functions by grouping 2-bits together into quaternary digits. This sort of quaternary encoded reversible realization of binary logic function requires half times input/output lines than the original binary reversible realization. Quaternary decoder, multiplexer, and demultiplexer are very important building blocks of quaternary digital systems. In this paper, we show reversible realization of these circuits using quaternary reversible gates like quaternary shift gates (QSG), quaternary controlled shift gates (QCSG), and quaternary Toffoli gates (QTG). We also show the realization of multi-digit QCSG and QTG using QSG and QCSG, which are realizable using liquid ion-trap quantum technology and other reversible technologies.
Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible
4×1multiplexer and
1×4demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversible
n×1multiplexer and
1×ndemultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.
Abstract In recent years, ternary reversible logic has become a promising paradigm for advancing low-power, high-performance quantum digital systems that preserve information and are energy efficient. This paper focuses on two primary objectives: first, the efficient realization of ternary reversible
3×1 3 × 1 multiplexers and
1×3 1 × 3 demultiplexers using quantum gates, specifically 1-qutrit Shift and 3-qutrit Controlled Feynman gates, and second, the design of generalized
n×1 n × 1 multiplexers and
1×n 1 × n demultiplexers. The proposed
9×1 9 × 1 multiplexer we propose in this study has demonstrated notable improvements in terms of quantum cost (20%), depth (18%), number of constant inputs (60%), and garbage outputs (30%), while the proposed
1×9 1 × 9 demultiplexer shows a 20% reduction in quantum cost, a 18% reduction in depth, a 33% reduction in constant inputs, and a 50% reduction in garbage outputs, compared to the most efficient existing designs. These optimizations represent an important step forward in the development of more efficient ternary and quantum reversible logic circuits, advancing the scalability of quantum systems.
Quaternary encoded binary circuits are more compact than their binary counterpart. Although several methods for designing binary reversible sequential circuits are presented, to the best of our knowledge, no design method for quaternary reversible sequential circuits has yet been reported in the literature. In this paper, we propose a design method for quaternary sequential circuits where the present state outputs are directly fedback to the next state determination circuit and that circuit is realized using QGFSOP expression as a cascade of one-digit, M-S, Feynman, and Toffoli gates. We also develop methods for making the sequential circuit falling-edge triggered and presettable using a quaternary Fred kin gate. As design examples, we present designs for up/down counters and universal registers. As there are no previous designs of quaternary sequential circuits, the closest comparison is made with designs of two-digit quaternary counter and universal register with designs of equivalent four-bit binary counter and universal register, respectively. In comparison to the equivalent binary designs, the proposed method requires less ancilla inputs with an increase in quantum cost.