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IEEE Computer Society Annual Symposium on VLSI

Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression

Mozammel H. A. Khan, Himanshu Thapliyal

Published Jul 1, 2015• 4 citations

Abstract

Quaternary encoded binary circuits are more compact than their binary counterpart. Although several methods for designing binary reversible sequential circuits are presented, to the best of our knowledge, no design method for quaternary reversible sequential circuits has yet been reported in the literature. In this paper, we propose a design method for quaternary sequential circuits where the present state outputs are directly fedback to the next state determination circuit and that circuit is realized using QGFSOP expression as a cascade of one-digit, M-S, Feynman, and Toffoli gates. We also develop methods for making the sequential circuit falling-edge triggered and presettable using a quaternary Fred kin gate. As design examples, we present designs for up/down counters and universal registers. As there are no previous designs of quaternary sequential circuits, the closest comparison is made with designs of two-digit quaternary counter and universal register with designs of equivalent four-bit binary counter and universal register, respectively. In comparison to the equivalent binary designs, the proposed method requires less ancilla inputs with an increase in quantum cost.

DOI: 10.1109/isvlsi.2015.53

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Ternary reversible logic functions are generally represented as ternary Galois field sum of products (TGFSOP) expressions and the TGFSOP expressions are mapped to reversible circuits using cascades of Feynman and Toffoli gates. Although a ternary logic function with a large number of variables can be minimized as a TGFSOP expression, the process is computationally expensive and the resulting reversible circuit tends to have a high quantum cost and ancilla inputs. To overcome these limitations, in this work we propose a new method of representing ternary reversible logic functions as Max of Min-terms (Max-Min) expressions, which can be mapped to a reversible circuit using multiple-controlled unary gates requiring lower quantum cost and fewer ancilla inputs. We propose a map-based minimization method for Max-Min expressions of up to four variables focusing on restrictions of the reversible circuit mapping technique.

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