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IEEE International Symposium on Multiple-Valued Logic (ISMVL)

Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits

Mozammel H. A. Khan

Published May 1, 2008• 20 citations
Publisher

Abstract

Quaternary logic is very suitable for encoded realization of binary logic functions by grouping 2-bits together into quaternary digits. This sort of quaternary encoded reversible realization of binary logic function requires half times input/output lines than the original binary reversible realization. Quaternary decoder, multiplexer, and demultiplexer are very important building blocks of quaternary digital systems. In this paper, we show reversible realization of these circuits using quaternary reversible gates like quaternary shift gates (QSG), quaternary controlled shift gates (QCSG), and quaternary Toffoli gates (QTG). We also show the realization of multi-digit QCSG and QTG using QSG and QCSG, which are realizable using liquid ion-trap quantum technology and other reversible technologies.

DOI
10.1109/ismvl.2008.33

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Quaternary reversible logic is very suitable for encoded realization of binary reversible logic functions by grouping two bits together into quaternary digits. Quaternary multiplexer and demultiplexer circuits are very important building blocks of quaternary digital systems. In this paper, we show reversible realizations of 4x1 multiplexer and 1x4 demultiplexer circuits on the top of liquid ion-trap realizable 1x1 and Muthukrishnan-Stroud gates. Then we show scalable architectures for design of mx1 multiplexer and 1xm demultiplexer circuits using 4x1 multiplexers and 1x4 demultiplexers, respectively, where m les 4nand n is the number of selection inputs. The proposed realizations of reversible multiplexer and demultiplexer circuits are more efficient than the earlier realizations in terms of number of primitive gates and number of ancilla inputs required.
Quaternary encoded binary circuits are more compact than their binary counterpart. Although several methods for designing binary reversible sequential circuits are presented, to the best of our knowledge, no design method for quaternary reversible sequential circuits has yet been reported in the literature. In this paper, we propose a design method for quaternary sequential circuits where the present state outputs are directly fedback to the next state determination circuit and that circuit is realized using QGFSOP expression as a cascade of one-digit, M-S, Feynman, and Toffoli gates. We also develop methods for making the sequential circuit falling-edge triggered and presettable using a quaternary Fred kin gate. As design examples, we present designs for up/down counters and universal registers. As there are no previous designs of quaternary sequential circuits, the closest comparison is made with designs of two-digit quaternary counter and universal register with designs of equivalent four-bit binary counter and universal register, respectively. In comparison to the equivalent binary designs, the proposed method requires less ancilla inputs with an increase in quantum cost.
Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors’ performance. A new scalable realization of quaternary reversible4×14\times 14×1multiplexer and1×41\times 41×4demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversiblen×1n\times 1n×1multiplexer and1×n1\times n1×ndemultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.
Galois field sum of products (GFSOP) has been found to be very promising for reversible/quantum implementation of multiplevalued logic. In this paper, we show nine quaternary Galois field expansions, using which quaternary Galois field decision diagrams (QGFDD) can be constructed. Flattening of the QGFDD generates quaternary GFSOP (QGFSOP). These QGFSOP can be implemented as cascade of quaternary 1-qudit gates and multi-qudit Feynman and Toffoli gates. We also show the realization of quaternary Feynman and Toffoli gates using liquid ion-trap realizable 1-qudit gates and 2-qudit Muthukrishnan-Stroud gates. Besides the quaternary functions, this approach can also be used for synthesis of encoded binary functions by grouping 2-bits together into quaternary value. For this purpose, we show binary-to-quaternary encoder and quaternary-to-binary decoder circuits using quaternary 1-qudit gates and 2-qudit Muthukrishnan-Stroud gates.