In recent years, reversible logic has emerged as a promising technology withapplications spanning low-power CMOS, quantum computing, nanotechnology, andoptical computing. Quantum computing, in particular, relies on reversible logic for itsrealization. The construction of low-power and low-loss computational structures iscrucial for developing arithmetic circuits used in quantum computation, nanotechnology,and other low-power digital circuits. This work presents optimized one-digit BCD addersand carries skip BCD adders using new reversible logic gates. The proposed approachaims to minimize quantum cost and optimize performance compared to existing circuits,focusing on reducing the number of reversible gates used and minimizing garbage outputsproduced. The objective is to design faster BCD adders and provide a foundation forbuilding the decimal Arithmetic Logic Unit (ALU) of a Quantum CPU. The work isimplemented using Hardware Description Language (HDL), with Simulation & Synthesisconducted on Xilinx ISE. The design targets the Xilinx Spartan 3E FPGA device. Thisresearch contributes to the advancement of efficient and high-performance arithmeticcircuits suitable for emerging technologies such as quantum computing andnanotechnology.
In recent years, reversible logic has emerged as a promising technology withapplications spanning low-power CMOS, quantum computing, nanotechnology, andoptical computing. Quantum computing, in particular, relies on reversible logic for itsrealization. The construction of low-power and low-loss computational structures iscrucial for developing arithmetic circuits used in quantum computation, nanotechnology,and other low-power digital circuits. This work presents optimized one-digit BCD addersand carries skip BCD adders using new reversible logic gates. The proposed approachaims to minimize quantum cost and optimize performance compared to existing circuits,focusing on reducing the number of reversible gates used and minimizing garbage outputsproduced. The objective is to design faster BCD adders and provide a foundation forbuilding the decimal Arithmetic Logic Unit (ALU) of a Quantum CPU. The work isimplemented using Hardware Description Language (HDL), with Simulation & Synthesisconducted on Xilinx ISE. The design targets the Xilinx Spartan 3E FPGA device. Thisresearch contributes to the advancement of efficient and high-performance arithmeticcircuits suitable for emerging technologies such as quantum computing andnanotechnology.
The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently perform BCD addition and implement the required correction logic while maintaining full reversibility. Evaluation results indicate that the proposed designs surpass existing reversible BCD adders, achieving best-case average improvements of 85.12% in delay and 30.75% in quantum cost. These advancements demonstrate the potential of the proposed adders for integration into future quantum-based arithmetic units and scalable reversible computing systems. Moreover, analysis of real banking transaction data underscores the practical importance of BCD addition and its widespread use in accurate and efficient monetary computations.
Reversible computing has emerged as a promising solution for reducing energy dissipation in digital systems by addressing the fundamental limitations caused by information loss.Quaternary reversible logic, which uses multi-valued representations, provides higher information density, reduced interconnect complexity, and better scalability when compared to conventional binary logic.This work presents the design and implementation of a quaternary reversible Arithmetic Logic Unit (ALU) that integrates essential computational modules, including arithmetic units, logical units, memory units, decoders, and multiplexers.The proposed architecture supports efficient data routing and precise operation control through a scalable control unit and a selection-line-based design approach.The designed ALU demonstrates reduced quantum cost, fewer garbage outputs, and minimized constant inputs in comparison with existing reversible ALU designs, while remaining compatible with larger reversible and quantum computing architectures.Simulation results and comparative analysis validate the improved efficiency and low-power potential of the proposed system, making it suitable for next-generation computing applications.The complete design is implemented using Verilog HDL and synthesized and simulated using Xilinx Vivado Design Suite 2025.
Reversible logic provides a foundation for nextgeneration computing systems, particularly in quantum and emerging nanotechnology-based architectures. Unlike conventional logic, reversible gates preserve information and support backward computation, making them crucial for designing quantum circuits. This paper introduces a reversible Arithmetic and Logic Unit (ALU) that performs eight fundamental operations-AND, OR, NOT, XOR, addition, subtraction, increment, and decrement-using Fredkin, Peres, TR, and modified Fredkin gates. A dedicated control unit manages operation selection, ensuring functional flexibility and circuit efficiency. The proposed design achieves significant improvements by minimizing ancilla inputs, quantum cost and garbage outputs, resulting in a total quantum cost of 71 and contains 16 reversible gates and 14 garbage outputs. The architecture was modeled and verified using Xilinx Vivado HLS and ISE 14.7, and implemented on the Nexys A7 (Artix-7) FPGA platform. Comparative analysis demonstrates better efficiency than existing reversible ALU designs, establishing the proposed circuit as a strong candidate for quantum computing and other advanced computing paradigms.
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Next, a novel 3*3 programmable UPG gate capable of calculating the fundamental logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, nbit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, 4*4 reversible gate is presented and verified which is capable of producing the calculations necessary for two-bit comparisons. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. Then, two novel 4*4 reversible logic gates (MRG and PAOG) are proposed with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. A 5*5 structure (MG) is proposed that extends the capabilities of both the MRG and PAOG. The comparator designs are verified and its advantages to previous designs are discussed. Then, reversible implementations of ripple-carry, carry-select and Kogge-Stone carry look-ahead adders are analyzed and compared. Next, implementations of the Kogge-Stone adder with sparsity-4, 8 and 16 were designed, verified and compared. The enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders was selected as the best design, and its implemented in the design of a 32-bit arithmetic logic unit is demonstrated. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed.
Within this paper, the authors introduce a new cost optimized quantum Binary-Coded Decimal (BCD) adder circuit that utilizes reversible gates as its building blocks. The newly proposed quantum BCD adder is specifically constructed with the inclusion of double Peres gates (DPG), Peres gates (PG), BJN gates, Feynman gates (FG), and reversible NOT gates. To bring this idea to life, we undertook the design and implementation of the proposed circuit using the Qiskit simulator provided by the IBM Quantum Computing lab. Our evaluation of the newly optimized BCD adder circuit yielded the following metrics, the quantum cost of 47, the constant input of 8, garbage output of 12, and a delay of 10. When compared to previously reported results, we observed significant improvements in various aspects, with a 25.39% reduction in quantum cost, a 28.57% decrease in constant input, and a 36.84% reduction in garbage output.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.