Reversible quantum computer is gaining interest for the future computer system. With the advent of quantum computer and reversible logic, design and implementation of all devices has received more attention. BCD digit adder is the basic unit of the more precise decimal computer arithmetic. The research objective is to increase speed of operation for addition of BCD numbers while minimizing the power dissipation by using reversible gates. This paper proposes one new reversible logic gate MAS. The MAS gate can be used as full adder and also reduces the number of garbage outputs. It can also be used as Copying Circuit to increase fan-out because fan-out is not allowed in reversible circuits. This paper also proposes a novel reversible design of 2 digit BCD full adder. The simulation result of 2 digit BCD adder on ModelSim are also included.
Reversible quantum computer is gaining interest for the future computer system. With the advent of quantum computer and reversible logic, design and implementation of all devices has received more attention. BCD digit adder is the basic unit of the more precise decimal computer arithmetic. The research objective is to increase speed of operation for addition of BCD numbers while minimizing the power dissipation by using reversible gates. This paper proposes one new reversible logic gate MAS. The MAS gate can be used as full adder and also reduces the number of garbage outputs. It can also be used as Copying Circuit to increase fan-out because fan-out is not allowed in reversible circuits. This paper also proposes a novel reversible design of 2 digit BCD full adder. The simulation result of 2 digit BCD adder on ModelSim are also included.
Reversible quantum computer is the best choice for the future computer system. With the advent of quantum computer and reversible logic, design and implementation of all devices has received more attention. BCD digit adder is the basic unit of the more precise decimal computer arithmetic. Several proposals have been given for the BCD adders. This paper proposes a reversible implementation of 2:1 vector MUX and a combined BCD Adder / Subtractor. This paper can be extended to execute more complex operations using reversible logic.
Reversible logic is one of the emerging computational methodologies which assures zero power dissipation through theoretical laws of thermodynamics. It has received significant interest in application on quantum computing, nanotechnologies and low power computing devices. In this work, we present a reversible logic implementation for Binary Coded Decimal (BCD) adder which is designed to obtain lowest quantum cost value. Other parameters such as ancilla input, garbage output and delay are kept at minimal. Experiment result shows that the proposed work outperforms other designs in terms of quantum cost. Considering for a 1 digit BCD adder, it has a 4% improvement in terms of quantum cost compared to the current best existing ones. The improvement range increases as the BCD digit becomes larger.
Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word. Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design. The principal objective of this work is to argue for quantum implementation of various reversible logic gates by using C-NOT, Controlled-V and Controlled-V+ gates. The present work presents Binary coded decimal adder (BCD) in terms of number of gates, garbage outputs, quantum cost, delay and hardware complexity compared to existing design.
In recent years, reversible logic has emerged as a promising technology withapplications spanning low-power CMOS, quantum computing, nanotechnology, andoptical computing. Quantum computing, in particular, relies on reversible logic for itsrealization. The construction of low-power and low-loss computational structures iscrucial for developing arithmetic circuits used in quantum computation, nanotechnology,and other low-power digital circuits. This work presents optimized one-digit BCD addersand carries skip BCD adders using new reversible logic gates. The proposed approachaims to minimize quantum cost and optimize performance compared to existing circuits,focusing on reducing the number of reversible gates used and minimizing garbage outputsproduced. The objective is to design faster BCD adders and provide a foundation forbuilding the decimal Arithmetic Logic Unit (ALU) of a Quantum CPU. The work isimplemented using Hardware Description Language (HDL), with Simulation & Synthesisconducted on Xilinx ISE. The design targets the Xilinx Spartan 3E FPGA device. Thisresearch contributes to the advancement of efficient and high-performance arithmeticcircuits suitable for emerging technologies such as quantum computing andnanotechnology.
The quantum and reversible paradigm merges the principles of quantum mechanics and reversible computation to enable information-preserving processing. It supports next-generation computing architectures that provide improved scalability and enhanced computational efficiency. Within these architectures, the decimal adder is a key arithmetic component, particularly for Binary Coded Decimal (BCD) operations widely used in financial and commercial systems. However, most reversible BCD adders focus primarily on quantum and reversible metrics, overlooking the critical influence of delay, which makes balanced optimization a significant challenge. This paper presents two reversible BCD adder designs optimized for both delay and quantum cost. One design integrates the decimal carry-skip technique to improve the overall delay. Using reversible logic gates, the proposed architectures efficiently perform BCD addition and implement the required correction logic while maintaining full reversibility. Evaluation results indicate that the proposed designs surpass existing reversible BCD adders, achieving best-case average improvements of 85.12% in delay and 30.75% in quantum cost. These advancements demonstrate the potential of the proposed adders for integration into future quantum-based arithmetic units and scalable reversible computing systems. Moreover, analysis of real banking transaction data underscores the practical importance of BCD addition and its widespread use in accurate and efficient monetary computations.
Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this work, we present a class of new designs for reversible binary and BCD adder circuits. The proposed designs are primarily optimized for the number of ancilla inputs and the number of garbage outputs and are designed for possible best values for the quantum cost and delay. In reversible circuits, in addition to the primary inputs, some constant input bits are used to realize different logic functions which are referred to as ancilla inputs and are overheads that need to be reduced. Further, the garbage outputs which do not contribute to any useful computations but are needed to maintain reversibility are also overheads that need to be reduced in reversible designs. First, we propose two new designs for the reversible ripple carry adder: (i) one with no input carry c 0 and no ancilla input bits, and (ii) one with input carry c 0 and no ancilla input bits. The proposed reversible ripple carry adder designs with no ancilla input bits have less quantum cost and logic depth (delay) compared to their existing counterparts in the literature. In these designs, the quantum cost and delay are reduced by deriving designs based on the reversible Peres gate and the TR gate. Next, four new designs for the reversible BCD adder are presented based on the following two approaches: (i) the addition is performed in binary mode and correction is applied to convert to BCD when required through detection and correction, and (ii) the addition is performed in binary mode and the result is always converted using a binary to BCD converter. The proposed reversible binary and BCD adders can be applied in a wide variety of digital signal processing applications and constitute important design components of reversible computing.