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Electronics and Communications in Japan (Part I Communications)

Carry time of magnetically coupled Josephson adder circuits

Hajime Yamada, Yoshichika Ichimiya, Akira Ishida

Published Jan 1, 1984• 1 citation
Publisher

Abstract

Abstract A carry circuit for Josephson adder has been studied and tested experimentally. For carry calculation, a ripple carry process by asymmetrical interferometric majority gates is employed because it can reduce the gate number‐add time products compared with carry look ahead process by conventional OR‐AND gates. Add time measurement has been performed with these carry circuits connected to dummy sum circuits. Operation speed as fast as 740 ps was obtained for 16‐bit calculation, which shows excellent agreement with computer simulation. By the analysis, it has been clarified that the operation speed is limited by impedance mismatched input lines.

DOI
10.1002/ecja.4400670814

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IEEE Transactions on Applied Superconductivity•Mar 1, 1993•10 citations
Abstract A carry circuit for Josephson adder has been studied and tested experimentally. For carry calculation, a ripple carry process by asymmetrical interferometric majority gates is employed because it can reduce the gate number‐add time products compared with carry look ahead process by conventional OR‐AND gates. Add time measurement has been performed with these carry circuits connected to dummy sum circuits. Operation speed as fast as 740 ps was obtained for 16‐bit calculation, which shows excellent agreement with computer simulation. By the analysis, it has been clarified that the operation speed is limited by impedance mismatched input lines.
A Josephson two-bit full adder circuit with wide margin functional gates has been studied. The adder circuit is comprised of functional exclusive-OR (EXOR) gates for sum operation and majority gates for ripple carry operation. A wide margin EXOR gate was constructed with serial connection of two double-input asymmetrical interferometers (AILs), in which two input lines were coupled to the interferometers with such an arrangement that the input-induced magnetic fluxes electromagnetically cancel each other. For majority gates, gate-to-input coupling should be made uniform for all three inputs. For this purpose, three input lines were laid in parallel on the loop of triple-input planar interferometer, so that one of two outer lines ran along the loop outside the edge but returned along the inside and the other vice versa. By using these functional gates a full adder circuit can be constructed with only three gates/bits. Experimentally, the two-bit parallel adder circuit was fabricated by standard Pb-alloy technology with 5μm line width. Two-bit parallel full adder operation was successfully performed. Additionally, operating margin over ±10% for the bias was obtained for each gate.
Reversible logic has represented itself as a prominent technology which plays an important role in Quantum Computing. Theoretically Quantum Computers operates at high speed and consumes less power. Furthermore, Reversible logic can break the conventional speed of power trade-off. To prove this we are implementing Ripple Carry Adder and Carry Look Ahead Adder using reversible logic gates. The paper presents efficient adder circuits using Peres gate, New fault Tolerant gate and Double Feyman gate. The complexity, simulated outputs and the speed parameters for the adder circuit have been indicated using the Quartus II 9.1 edition and Modelsim tool. Moreover, the quantum algorithms can potentially solve NP-complete problems. Furthermore, doing high performance functions beyond the limit of deterministic computer systems is possible by only reversible logic. Quantum operations are unitary in nature which is reversible and hence the arithmetic operations like adders can be implemented using the reversible logic. Likewise, optimized block size, minimum ancillary bits, and one to one mappings of inputs and outputs are obtained in the reversible adder circuit, giving fan out as 1. Hence, the Ripple Carry Adder and Carry look Ahead Adder is providing complexity reduction and high speed, proving to be an efficient and important part in the development of arithmetic blocks of Quantum Computers.
Abstract This paper proposes a Josephson threshold logic circuit, which is best suited to high‐speed operations. Using the proposed circuit, the adder can be constructed by four Josephson elements. The scale of the circuit can be reduced both in the number of circuits and the number of logic stages, compared with the conventional Josephson logic circuits. The circuit is shown to be useful in the realization of the high‐speed and highly integrated adders and multipliers. Then it is demonstrated that the Josephson threshold logic circuit can be constructed by the magnetically coupled interferometer element, the current‐injection interferometer element and the direct‐coupled element. A typical circuit construction is shown with the adder as an example. To verify the correct operation of the Josephson threshold logic circuit, a 1‐bit adder by magnetically coupled interferometer elements was constructed by Nb‐Pb alloy process, and the operation of the circuit was verified.
A novel Josephson logic gate called the asymmetrical interferometer device (AID) is presented. It is composed of a pair of asymmetrical interferometers whose outputs are injected into a single junction. The interferometers are individually operated as two input OR and the single junction is worked as AND.(A + B) (C + D)operation is accomplished by only one AID gate. They have a serial fan-in capability due to their magnetic coupling scheme. The gate size is reduced by half, compared with the previous current injection logic (CIL) gate. With these AID gates, a high-speed two-bit dual rail adder circuit is configured, which provides the logic circuits performing with both true and complement inputs and without any timing circuits. The AID gate fabricated by standard 5-µm Pb-alloy technology showed a wide margin over ±20 percent that was in good agreement with statically designed characteristics. Experimental adder operation was also successfully performed.
We have designed, fabricated and experimentally demonstrated an 8-bit carry look-ahead adder using clockless AND and NIMPLY cells. A clockless cell is a logic cell without a clock input. Comprared to the circuit using only clocked cells, the circuit using clockless cells has fewer routing wires and splitters. Decrease of the numbers of wires and splitters can reduce the area of a circuit. The 8-bit adder core (without SFQ-to-DC and DC-to-SFQ converters, the clock generator and input and output shift registers for the high frequency test) has 3320 Josephson junctions (JJs) occupying the area of 1.84 mm2. It is designed for the target operation frequency is 10 GHz with 3 pipeline stages, and the delay from the clock input to the primary outputs of 74 ps at most at the bias voltage of 2.5 mV. The adder chip was fabricated using AIST 10-kA/cm2 Advanced Process (ADP2) and tested at low and high frequency with measured bias margins of +16%/+6%. The measured maximum frequency was 12.87 GHz.
The authors describe a novel Josephson adder based on the radix-2 signed-digit number representation. In the proposed adder, the addition operation can be carried out in a constant time independent of word length owing to the elimination of the carry propagation chain. A critical path for generating the sum signal can be completed through only three series gates. A carry signal and an intermediate sum signal for all digits in the adder are simultaneously generated in the first step, and the final sum signal is obtained in the second step. Features of the proposed adder are a simple construction, ultra-high speed, and low power consumption. The principle of constructing the adder with an 8 b word length using superconducting quantum interference devices (SQUIDs) is described in detail, and simulation results are presented. Results show that reliable operation can be achieved for the longest delay time of 120 ps for the 8 b adder.>