Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Magnetics

Josephson two-bit full adder utilizing wide margin functional gates

Yoshichika Ichimiya, Hironao YAMADA, Akira Ishida

Published May 1, 1983• 7 citations
Publisher

Abstract

A Josephson two-bit full adder circuit with wide margin functional gates has been studied. The adder circuit is comprised of functional exclusive-OR (EXOR) gates for sum operation and majority gates for ripple carry operation. A wide margin EXOR gate was constructed with serial connection of two double-input asymmetrical interferometers (AILs), in which two input lines were coupled to the interferometers with such an arrangement that the input-induced magnetic fluxes electromagnetically cancel each other. For majority gates, gate-to-input coupling should be made uniform for all three inputs. For this purpose, three input lines were laid in parallel on the loop of triple-input planar interferometer, so that one of two outer lines ran along the loop outside the edge but returned along the inside and the other vice versa. By using these functional gates a full adder circuit can be constructed with only three gates/bits. Experimentally, the two-bit parallel adder circuit was fabricated by standard Pb-alloy technology with 5μm line width. Two-bit parallel full adder operation was successfully performed. Additionally, operating margin over ±10% for the bias was obtained for each gate.

DOI
10.1109/tmag.1983.1062329

Related papers

Josephson dual rail two-bit adder circuit utilizing magnetically coupled OR-AND gates

Hirotaka Yamada, Yoshichika Ichimiya, Akira Ishida

A novel Josephson logic gate called the asymmetrical interferometer device (AID) is presented. It is composed of a pair of asymmetrical interferometers whose outputs are injected into a single junction. The interferometers are individually operated as two input OR and the single junction is worked as AND.(A + B) (C + D)operation is accomplished by only one AID gate. They have a serial fan-in capability due to their magnetic coupling scheme. The gate size is reduced by half, compared with the previous current injection logic (CIL) gate. With these AID gates, a high-speed two-bit dual rail adder circuit is configured, which provides the logic circuits performing with both true and complement inputs and without any timing circuits. The AID gate fabricated by standard 5-µm Pb-alloy technology showed a wide margin over ±20 percent that was in good agreement with statically designed characteristics. Experimental adder operation was also successfully performed.

IEEE Transactions on Electron Devices•Mar 1, 1984•5 citations

Direct-coupled Josephson full adder

J. H. Magerlein, L. N. Dunkleberger

We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.

IEEE Transactions on Magnetics•Jan 1, 1977•7 citations

A parallel full adder circuit using Josephson junctions

S. Hasuo, Hideo Suzuki, Kouichi Dazai

Detailed investigations have been carried out on a Josephson parallel full adder as an example of a functional circuit using Josephson junctions. This circuit can be constructed with fewer devices as compared with conventional Josephson adders. Two-junction interferometers (d.c.-SQUIDs) are utilized as switching elements of the circuit. Only (2N+1) d.c.-SQUIDs are required for construction of an N bit circuit. Discussions focus on design theory of the full adder circuit. An experimental 4 bit circuit operation is also demonstrated.

IEEE Journal of Solid-State Circuits•Feb 1, 1981•3 citations

Carry time of magnetically coupled Josephson adder circuits

Hajime Yamada, Yoshichika Ichimiya, Akira Ishida

Abstract A carry circuit for Josephson adder has been studied and tested experimentally. For carry calculation, a ripple carry process by asymmetrical interferometric majority gates is employed because it can reduce the gate number‐add time products compared with carry look ahead process by conventional OR‐AND gates. Add time measurement has been performed with these carry circuits connected to dummy sum circuits. Operation speed as fast as 740 ps was obtained for 16‐bit calculation, which shows excellent agreement with computer simulation. By the analysis, it has been clarified that the operation speed is limited by impedance mismatched input lines.

Electronics and Communications in Japan (Part I Communications)•Jan 1, 1984•1 citation

Bit-serial multiplier based on Josephson latching logic

A. Moopenn, E.R. Arambula, M.J. Lewis +1 more

The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics of Josephson circuits to achieve higher circuit functionality per gate by reducing gate complexity. To facilitate the multiplier design, logic simulation was performed using transistor-transistor-logic (TTL) equivalent gate models of voltage latching modified-variable-threshold-logic (MVTL) gates. A 4-b serial-parallel multiplier based on MVTL gates has been designed and fabricated in niobium. The basic timed-XOR and full adder circuits used in the multiplier were successfully tested. Preliminary testing of the multiplier indicated inadequate operating margin for a full functional test.>

IEEE Transactions on Applied Superconductivity•Mar 1, 1993•6 citations

A 4-bit×4-bit multiplier and 3-bit counter in Josephson threshold logic

Y. Hatano, Y. Harada, Kei Yamashita +2 more

A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.

IEEE Journal of Solid-State Circuits•Aug 1, 1987•14 citations
A Josephson two-bit full adder circuit with wide margin functional gates has been studied. The adder circuit is comprised of functional exclusive-OR (EXOR) gates for sum operation and majority gates for ripple carry operation. A wide margin EXOR gate was constructed with serial connection of two double-input asymmetrical interferometers (AILs), in which two input lines were coupled to the interferometers with such an arrangement that the input-induced magnetic fluxes electromagnetically cancel each other. For majority gates, gate-to-input coupling should be made uniform for all three inputs. For this purpose, three input lines were laid in parallel on the loop of triple-input planar interferometer, so that one of two outer lines ran along the loop outside the edge but returned along the inside and the other vice versa. By using these functional gates a full adder circuit can be constructed with only three gates/bits. Experimentally, the two-bit parallel adder circuit was fabricated by standard Pb-alloy technology with 5μm line width. Two-bit parallel full adder operation was successfully performed. Additionally, operating margin over ±10% for the bias was obtained for each gate.
A novel Josephson logic gate called the asymmetrical interferometer device (AID) is presented. It is composed of a pair of asymmetrical interferometers whose outputs are injected into a single junction. The interferometers are individually operated as two input OR and the single junction is worked as AND.(A + B) (C + D)operation is accomplished by only one AID gate. They have a serial fan-in capability due to their magnetic coupling scheme. The gate size is reduced by half, compared with the previous current injection logic (CIL) gate. With these AID gates, a high-speed two-bit dual rail adder circuit is configured, which provides the logic circuits performing with both true and complement inputs and without any timing circuits. The AID gate fabricated by standard 5-µm Pb-alloy technology showed a wide margin over ±20 percent that was in good agreement with statically designed characteristics. Experimental adder operation was also successfully performed.
We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.
Detailed investigations have been carried out on a Josephson parallel full adder as an example of a functional circuit using Josephson junctions. This circuit can be constructed with fewer devices as compared with conventional Josephson adders. Two-junction interferometers (d.c.-SQUIDs) are utilized as switching elements of the circuit. Only (2N+1) d.c.-SQUIDs are required for construction of an N bit circuit. Discussions focus on design theory of the full adder circuit. An experimental 4 bit circuit operation is also demonstrated.
Abstract A carry circuit for Josephson adder has been studied and tested experimentally. For carry calculation, a ripple carry process by asymmetrical interferometric majority gates is employed because it can reduce the gate number‐add time products compared with carry look ahead process by conventional OR‐AND gates. Add time measurement has been performed with these carry circuits connected to dummy sum circuits. Operation speed as fast as 740 ps was obtained for 16‐bit calculation, which shows excellent agreement with computer simulation. By the analysis, it has been clarified that the operation speed is limited by impedance mismatched input lines.
The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics of Josephson circuits to achieve higher circuit functionality per gate by reducing gate complexity. To facilitate the multiplier design, logic simulation was performed using transistor-transistor-logic (TTL) equivalent gate models of voltage latching modified-variable-threshold-logic (MVTL) gates. A 4-b serial-parallel multiplier based on MVTL gates has been designed and fabricated in niobium. The basic timed-XOR and full adder circuits used in the multiplier were successfully tested. Preliminary testing of the multiplier indicated inadequate operating margin for a full functional test.>
A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.