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IEEE Transactions on Applied Superconductivity

Bit-serial multiplier based on Josephson latching logic

A. Moopenn, E.R. Arambula, M.J. Lewis, Huang-Tian Chan

Published Mar 1, 1993• 6 citations
Publisher

Abstract

The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics of Josephson circuits to achieve higher circuit functionality per gate by reducing gate complexity. To facilitate the multiplier design, logic simulation was performed using transistor-transistor-logic (TTL) equivalent gate models of voltage latching modified-variable-threshold-logic (MVTL) gates. A 4-b serial-parallel multiplier based on MVTL gates has been designed and fabricated in niobium. The basic timed-XOR and full adder circuits used in the multiplier were successfully tested. Preliminary testing of the multiplier indicated inadequate operating margin for a full functional test.>

DOI
10.1109/77.233983

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IEICE Electronics Express•Jan 1, 2009•4 citations
The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics of Josephson circuits to achieve higher circuit functionality per gate by reducing gate complexity. To facilitate the multiplier design, logic simulation was performed using transistor-transistor-logic (TTL) equivalent gate models of voltage latching modified-variable-threshold-logic (MVTL) gates. A 4-b serial-parallel multiplier based on MVTL gates has been designed and fabricated in niobium. The basic timed-XOR and full adder circuits used in the multiplier were successfully tested. Preliminary testing of the multiplier indicated inadequate operating margin for a full functional test.>
High-speed operation of Josephson processors is demonstrated. They are a 4-b microprocessor, a 4-b processor, and an 8-b digital signal processor. Key technologies to realize these circuits are described from the viewpoint of circuit design. The technologies are a high-speed logic gate, named MVTL (modified variable threshold logic), and a three-phase sinusoidal power supply system. The MVTL gate has a large operating margin and high sensitivity. The MVTL gate family consists of OR, AND, 2/3 majority (MJ), and timed inverter (TI). Using these gates a variety of processors have been designed. These processors operate with three-phase power. The waveform is sinusoidal with DC-offset. This power supply system needs no latch and regulator circuit. This makes the processor very simple, and thus results in high-speed operation. To fabricate these processors, niobium junctions are very important, because they are reliable, uniform, controllable, and reproducible. High-speed gates, three-phase power supplies, and niobium junctions are indispensable for high-speed Josephson processors.
We have designed an SFQ pipeline multiplier using a cell-based design method. The cell-based design method enables us to expand the circuit-scale easily and is essential for the design of large-scale circuits. In the construction of the multiplier, a serial-parallel type was adopted. This type performs the partial products and the summation of the products in a bit-serial form. The multiplier designed here is a 3-bit serial-parallel structure with a seven-stage pipeline and is composed of destructive read-out (DRO) gates, nondestructive read-out (NDRO) gates and carry save serial adders (CSSA's). This circuit was fabricated by the NEC standard process. The number of Josephson Junctions is 1150. We have successfully tested the full operation with a bias margin of /spl plusmn/5.5%.
A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.
A high-throughput 4$\boldsymbol{\times }4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm\boldsymbol{^2},Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134, Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134,Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134\boldsymbol{\mu }W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40W, respectively. Although the switching speed of the Josephson junctions was reduced by 40W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40\boldsymbol{\%}$owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.
In this study, we designed, fabricated, and experimentally tested a Josephson latching driver (JLD), a superconductor-to-semiconductor interface circuit for use in Josephson-CMOS hybrid memory, utilizing a 10-kA/cm2Nb process. The JLD is composed of a voltage driver known as a Suzuki stack and a Josephson four-junction logic (4JL) gate that serves as a preamplifier. The basic structure is based on our previous design using the 2.5-kA/cm2Nb process. In this study, we optimized the critical current and the load resistance of the 4JL gate, taking into account the parameters of the Josephson junctions in the 10-kA/cm2process. In experiments with the fabricated test circuit, we confirmed the correct operation of the JLD (bit error rate−11) at a target frequency of 5 GHz. We also confirmed the correct function of multichannel JLDs, which were used as interface circuits in Josephson-CMOS hybrid memory, in a low-frequency test.
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.