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IEEE Journal of Solid-State Circuits

A 4-bit×4-bit multiplier and 3-bit counter in Josephson threshold logic

Y. Hatano, Y. Harada, Kei Yamashita, Y. Tarutani, Ushio KAWABE

Published Aug 1, 1987• 14 citations
Publisher

Abstract

A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.

DOI
10.1109/jssc.1987.1052778

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IEEE Transactions on Magnetics•Mar 1, 1991•0 citations
A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.
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Abstract This paper proposes a Josephson threshold logic circuit, which is best suited to high‐speed operations. Using the proposed circuit, the adder can be constructed by four Josephson elements. The scale of the circuit can be reduced both in the number of circuits and the number of logic stages, compared with the conventional Josephson logic circuits. The circuit is shown to be useful in the realization of the high‐speed and highly integrated adders and multipliers. Then it is demonstrated that the Josephson threshold logic circuit can be constructed by the magnetically coupled interferometer element, the current‐injection interferometer element and the direct‐coupled element. A typical circuit construction is shown with the adder as an example. To verify the correct operation of the Josephson threshold logic circuit, a 1‐bit adder by magnetically coupled interferometer elements was constructed by Nb‐Pb alloy process, and the operation of the circuit was verified.
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A high-throughput 4$\boldsymbol{\times }4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm\boldsymbol{^2},Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134, Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134,Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134\boldsymbol{\mu }W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40W, respectively. Although the switching speed of the Josephson junctions was reduced by 40W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40\boldsymbol{\%}$owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.
The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic (4JL) gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance mi). We have developed a speedup method in which an inductance is connected to Ri in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. 40 % speedup of the gate switching was demonstrated by a logic delay experiment using submicron NbN/MgO/NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.
A Josephson binary counter with nondestructive readout has been implemented and tested in both niobium and niobium nitride technology. Successful operation of the Nb version has been observed. The design incorporates an additional tapered-edge SiO/sub 2/ level in the Nb processing sequence, which increases interferometer inductance, decreases capacitance, and ensures that geometric resonances are as high in frequency as possible. This level has the added advantage of providing mask compatibility with the NbN process, as this level is skipped in the NbN flow, thereby compensating in part for the larger penetration depth of NbN. The counter cell is designed to be as compact as possible to minimize stray inductance and maximize top count rate and high count rate bias margins. A novel readout SQUID coupling layout that allows low read SQUID inductance and requires no holes in the groundplane is used. Coupling to the adjacent count SQUID is provided by a common control line level metallization, which directs count SQUID flux through the read SQUID loop. Nb versions of the circuit functioned as expected, but low device yield limited the longest chain of functioning stages to five. The NbN circuits did not function due to higher than predicted inductance values.