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IEEE Transactions on Applied Superconductivity

A speedup method of a high-speed direct-coupled Josephson logic gate

Masahiro Aoyagi, Hiroshi Nakagawa, I. Kurosawa, Hiroshi Akoh, S. Takada

Published Mar 1, 1993• 5 citations
Publisher

Abstract

The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connected to (R/sub i/) in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. A speedup of 40% in the gate switching was demonstrated by a logic delay experiment using submicron NbN-MgO-NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.>

DOI
10.1109/77.233978

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The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connected to (R/sub i/) in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. A speedup of 40% in the gate switching was demonstrated by a logic delay experiment using submicron NbN-MgO-NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.>
The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic (4JL) gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance mi). We have developed a speedup method in which an inductance is connected to Ri in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. 40 % speedup of the gate switching was demonstrated by a logic delay experiment using submicron NbN/MgO/NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.
A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.
Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10−16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.
We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.