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Applied Physics Letters

Delay measurement of experimental 2.5-μm Josephson current injection logic (CIL)

Tushar R. Gheewala

Published May 15, 1979• 11 citations
Publisher

Abstract

Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10−16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.

DOI
10.1063/1.90632

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Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10−16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.
The gate delay of a single CIL AND gate is measured with a Josephson sampler. The CIL gate consists of a CIL interferometer preceded by a three-junction SQUID isolation stage. The smallest delay observed was 6 ps. Simulation results and sampling measurements of a gate designed to switch to 3Vgare also reported. Processing variations precluded successful operation of the higher-voltage gate. The simulations suggest that this failure is due to the large difference of the average critical current from the design value. Scaling arguments show that for small-scale circuits high-speed operation with gate delays of a few picoseconds can be achieved with junction dimensions approximately equal to the Josephson penetration depth.
Logic delays of a current-switched latching gate called the Josephson atto-Weber switch and its use in a dc powered flip-flop module have been investigated. Experimental circuits with cascade chains of 31 gates were fabricated using 5-μm square lead alloy tunnel junctions. Delays were measured on both the latching and the unlatching chains. The experimental circuits demonstrate operation faster than those reported for other Josephson gate designs using the same linewidth. For the latching OR gate with fanout of 3, the shortest measured gate delay is 15 ps.
The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic (4JL) gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance mi). We have developed a speedup method in which an inductance is connected to Ri in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. 40 % speedup of the gate switching was demonstrated by a logic delay experiment using submicron NbN/MgO/NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.
The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connected to (R/sub i/) in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. A speedup of 40% in the gate switching was demonstrated by a logic delay experiment using submicron NbN-MgO-NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.>
For a given level of overdrive, there exists a minimum-width control-current pulse that must be applied to switch a Josephson logic gate. Determination of this minimum pulsewidth is useful in setting limits on the speed of various Josephson circuit configurations and also in finding the narrowest pulse that a Josephson-junction gate can detect when it is employed as a pulse detector. The minimum control-current pulsewidth is a strong function of the overdrive factor of the control current. It scales as(C/I_{m})^{1/2}, where Imis the junction critical current, andCis the capacitance, and is on the order of 10 ps for Josephson quantum interferometers in 5-µm technology. Computer simulations have been done to find the dependence of minimum control-current pulsewidths on overdrive magnitude for a single-junction gate and for two- and three-junction interferometers. Analytic expressions of the minimum control-current pulsewidth that are in good agreement with simulations have been obtained for these three types of Josephson logic gates.