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IEEE Transactions on Magnetics

High-speed measurements of single gates; Higher-voltage gates

H.L. Ko, D. Petersen, T. Van Duzer

Published Mar 1, 1987• 5 citations
Publisher

Abstract

The gate delay of a single CIL AND gate is measured with a Josephson sampler. The CIL gate consists of a CIL interferometer preceded by a three-junction SQUID isolation stage. The smallest delay observed was 6 ps. Simulation results and sampling measurements of a gate designed to switch to 3Vgare also reported. Processing variations precluded successful operation of the higher-voltage gate. The simulations suggest that this failure is due to the large difference of the average critical current from the design value. Scaling arguments show that for small-scale circuits high-speed operation with gate delays of a few picoseconds can be achieved with junction dimensions approximately equal to the Josephson penetration depth.

DOI
10.1109/tmag.1987.1064967

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The gate delay of a single CIL AND gate is measured with a Josephson sampler. The CIL gate consists of a CIL interferometer preceded by a three-junction SQUID isolation stage. The smallest delay observed was 6 ps. Simulation results and sampling measurements of a gate designed to switch to 3Vgare also reported. Processing variations precluded successful operation of the higher-voltage gate. The simulations suggest that this failure is due to the large difference of the average critical current from the design value. Scaling arguments show that for small-scale circuits high-speed operation with gate delays of a few picoseconds can be achieved with junction dimensions approximately equal to the Josephson penetration depth.
Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10−16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.
A multi-input AND gate composed of multiple stages, each with a three-junction interferometer and a single junction (ladder structure) is proposed. The number of inputs to this multi-input with multi-stage AND gate can easily be extended by systematically increasing the number of stages without decreasing the operating margin. The design and experimental results are described. Operating margins of the six-input AND gate were +or-30% (from simulation) and +or-20% (from experiment). The operating speed, simulated for 2.5- mu m-diameter junctions, was 60 ps, whereas the measured speed was 130 ps. The difference seems to be due to circuit parameter spread because the chip used for measuring the speed had large critical current deviation.>
It has generally been assumed that the switching dynamics of Josephson logic devices can be well approximated by treating the Josephson device as a capacitatively-shunted switch which opens instantaneously when a control current crosses threshold. In this approximation, the switching delay is proportional to RC, where R = load resistance and C = device capacitance. However, we show here that the above approximation is quite incorrect in the technologically important case of logic interferometers in which resonances are suppressed by internal damping. We treat in detail the case of damped two-junction interferometers with step-function control current. Analysis of the equations of motion shows that in addition to the RC delay there is an initial turn-on delay during which the output voltage is very small, and which is most pronounced for heavy internal damping. It consists of the time required for the difference in phase between the two junctions to increase to a critical value, followed by approximately the first half-cycle of growth of the average of the junction phases. The turn-on delay is a strong function of overdrive, (i.e., the factor by which the control current amplitude exceeds threshold), being smallest at large overdrives, and scales as (C/i0)1/2, where i0= junction critical current. Hence it can be reduced by miniaturization and/or increased junction current density. For parameter values typical of 5μm Josephson circuit technology, the turn-on delay is on the order of 10pS at large overdrives (≃2).
A versatile current-switched gate is described which consists of two Josephson tunnel junctions and a small resistor in a loop. The directly combined bias and control currents flow through one junction in the zero-voltage state, causing the switching. The second junction and the resistor provide isolation between input and output after switching. The switching speed of a few tens of picoseconds and the microwatt power dissipation are comparable to those of other present designs. The design is particularly simple, compact, and easy to fabricate.
At the typical operating temperature of 4.2 K, the theoretical upper limit of the clock frequency of the Low-Temperature Superconductive (LTS) Nb based Rapid Single Flux Quantum (RSFQ) digital circuits is several hundred GHz. Nevertheless, the few middle-scale RSFQ circuits reported on up to now operate at only some tens of GHz. An important performance-limiting factor is in this case the clock signal distribution, so nowadays asynchronous RSFQ designs are often considered. Our previous studies have shown that it is an important advantage of a given asynchronous RSFQ cell library to contain gates with tunable delays. We have already shown by simulations that the RSFQ gate delays are best adjusted by changing the Stewart-McCumber parameter /spl beta//sub c/ of the Josephson junctions-this method tunes the delay within a large interval of values while scarcely affecting the margins and the fabrication yield of the RSFQ gates. In order to prove this statement experimentally, we have designed, fabricated, and tested several ring-shaped oscillators with identical topologies but different Stewart-McCumber parameters of the Josephson junctions. Their operating speeds and margins are measured and compared.
Logic delays of a current-switched latching gate called the Josephson atto-Weber switch and its use in a dc powered flip-flop module have been investigated. Experimental circuits with cascade chains of 31 gates were fabricated using 5-μm square lead alloy tunnel junctions. Delays were measured on both the latching and the unlatching chains. The experimental circuits demonstrate operation faster than those reported for other Josephson gate designs using the same linewidth. For the latching OR gate with fanout of 3, the shortest measured gate delay is 15 ps.