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Applied Physics Letters

Logic delays of 5-μm current-switched Josephson gates

S. S. Pei

Published Apr 15, 1982• 11 citations
Publisher

Abstract

Logic delays of a current-switched latching gate called the Josephson atto-Weber switch and its use in a dc powered flip-flop module have been investigated. Experimental circuits with cascade chains of 31 gates were fabricated using 5-μm square lead alloy tunnel junctions. Delays were measured on both the latching and the unlatching chains. The experimental circuits demonstrate operation faster than those reported for other Josephson gate designs using the same linewidth. For the latching OR gate with fanout of 3, the shortest measured gate delay is 15 ps.

DOI
10.1063/1.93211

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Logic delays of a current-switched latching gate called the Josephson atto-Weber switch and its use in a dc powered flip-flop module have been investigated. Experimental circuits with cascade chains of 31 gates were fabricated using 5-μm square lead alloy tunnel junctions. Delays were measured on both the latching and the unlatching chains. The experimental circuits demonstrate operation faster than those reported for other Josephson gate designs using the same linewidth. For the latching OR gate with fanout of 3, the shortest measured gate delay is 15 ps.
Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10−16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.
The authors present the experimental results for the switching delay of a dc-biased nonlatching Josephson gate (a coupled-superconducting quantum interference device gate). The measurement is executed by the use of a ring oscillator (RO) method. A frequency-to-voltage converter is used to evaluate the oscillation frequency of the RO. The circuit is designed and fabricated using a 2.5-kA/cm/sup 2/ Nb/AlO/sub x//Nb Josephson junction technology. The results show the minimum switching delay of 18 ps.
We present the experimental implementation of an RS flip-flop (RS-FF) composed of dc-biased coupled-SQUID (C-SQUID) gates. The C-SQUID gate is a combination of a single-junction SQUID and a double-junction SQUID. This gate utilizes nonhysteretic Josephson junctions and it is operated in nonlatching mode with dc-biasing. Several logical functions are able to be realized with a C-SQUID gate by adjusting the input bias and the input signal levels. The speed performance of the gate is evaluated by simulation for ring oscillators, and the minimum switching delay of 6.5 ps/stage is obtained under Josephson critical current density of 10 kA/cm/sup 2/. We have fabricated the RS-FF composed of two C-SQUID NOR gates. The circuit is integrated using a Nb/AlO/sub x//Nb junction technology and its operation is demonstrated experimentally.
A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.
We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.