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IEEE Journal of Solid-State Circuits

Proposal of dual-powered superconducting logic circuits

Hironao YAMADA, Toshiro Tanaka

Published Aug 1, 1985• 4 citations
Publisher

Abstract

A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.

DOI
10.1109/jssc.1985.1052396

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A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.
High-speed operation of Josephson processors is demonstrated. They are a 4-b microprocessor, a 4-b processor, and an 8-b digital signal processor. Key technologies to realize these circuits are described from the viewpoint of circuit design. The technologies are a high-speed logic gate, named MVTL (modified variable threshold logic), and a three-phase sinusoidal power supply system. The MVTL gate has a large operating margin and high sensitivity. The MVTL gate family consists of OR, AND, 2/3 majority (MJ), and timed inverter (TI). Using these gates a variety of processors have been designed. These processors operate with three-phase power. The waveform is sinusoidal with DC-offset. This power supply system needs no latch and regulator circuit. This makes the processor very simple, and thus results in high-speed operation. To fabricate these processors, niobium junctions are very important, because they are reliable, uniform, controllable, and reproducible. High-speed gates, three-phase power supplies, and niobium junctions are indispensable for high-speed Josephson processors.
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We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.
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A new dc-powered Josephson latch has been designed and experimentally investigated.A latch is defined as a digital circuit in which information can be stored in a controlled manner. The latch we describe here consists of a nonlatching interferometer in series with a superconducting storage loop containing a second interferometer. Within the nominal operating region the latch has only two stable states and it does not display the problem of falling into a stable faulty state, in which the latch would respond to neither of its inputs (SET or RESET). Computer simulations using nominal 2.5-μm technology-device models indicate that the latch changes state in about 80 ps.
This paper describes the development of a dc-powered Josephson logic family that uses hybrid unlatching flip-flop logic elements (Huffles). The Huffle circuit used in this study is modified by adding a parallel resistor to the original Hebard-type Huffle circuit. Analysis of the circuit's operation shows that the undesirable hung-up phenomena are prevented by this modification. Based on the result of the analysis, the circuit's parameters are derived and a typical operating margin of /spl plusmn/26% is obtained. Besides AND/OR operations using a threshold logic operation, two-input exclusive OR (XOR), two-input multiplexor (MUX), and three-input majority (MAJ) operations are realized using a Huffle gate in which 2-Josephson-interferometers (2JI) in the standard Huffle gate are replaced by stacked-2JI's. Thus, a Huffle logic family, formed from NOT, AND, OR, XOR, MUX, MAJ, and flip-flop (FF), are constructed. By using this Huffle logic family, a 6-b arithmetic logic operating unit (ALU), a 6-b analog-to-digital converter (ADC), and a 6-b gray-to-binary converter (GBC) have been successfully operated. During high-speed testing, a 1-b comparator was operated up to an input bandwidth of 6 GHz.