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Applied Physics Letters

A Josephson dc-powered latch

Sang H. Dhong, Tushar R. Gheewala

Published Jun 1, 1981• 6 citations
Publisher

Abstract

A new dc-powered Josephson latch has been designed and experimentally investigated.A latch is defined as a digital circuit in which information can be stored in a controlled manner. The latch we describe here consists of a nonlatching interferometer in series with a superconducting storage loop containing a second interferometer. Within the nominal operating region the latch has only two stable states and it does not display the problem of falling into a stable faulty state, in which the latch would respond to neither of its inputs (SET or RESET). Computer simulations using nominal 2.5-μm technology-device models indicate that the latch changes state in about 80 ps.

DOI
10.1063/1.92188

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IEEE Journal of Solid-State Circuits•Oct 1, 1979•2 citations
A new dc-powered Josephson latch has been designed and experimentally investigated.A latch is defined as a digital circuit in which information can be stored in a controlled manner. The latch we describe here consists of a nonlatching interferometer in series with a superconducting storage loop containing a second interferometer. Within the nominal operating region the latch has only two stable states and it does not display the problem of falling into a stable faulty state, in which the latch would respond to neither of its inputs (SET or RESET). Computer simulations using nominal 2.5-μm technology-device models indicate that the latch changes state in about 80 ps.
A new current-injection Josephson latch employing a single-flux quantum is proposed. It has a master-slave circuit configuration and operates under ac power supply. In the circuit, data are stored as a circulating current in a superconducting loop consisting of a single junction and inductances. A two-junction interferometer gate directly coupled to the loop reads out the stored data. Dual-rail signals are generated from the read-out data by Josephson junctions and resister-coupled Josephson logic gates. The isolation between a master circuit and a slave circuit is realized using high-impedance states in the Josephson junctions. The circuit design and computer-simulation results on the circuit operation are described in this paper.
A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.
A Josephson superconducting quantum interference device (SQUID) digital logic family was developed that uses the R/sub nn/ region of a Josephson junction (JJ) to compensate for variations in where R/sub nn/ is the effective resistance of a JJ in the linear I-V region beyond the gap. The basic compensating junction logic (CJL) circuit is two 2-input-OR 1-2-1 interferometer isolators that, when switched, inject current into a 2-input-AND 1-2-1 interferometer. The R/sub nn/ region of several JJs is used in series with a resistor to set the current from the power supply to the 2-input-OR interferometers. The 2-input-AND interferometer is implemented with both current injection and magnetic coupling. The latch circuit uses both current injection and magnetic coupling design techniques to increase the range of I/sub O/, inductance, and resistance variation over which the latch will function correctly. Experimental measurements of CJL circuits are described.>
The dynamic behavior of Josephson devices, in particular interferometers, is investigated with simple approximations and computer simulations. It is shown that in the latching and in the nonlatching operation modes, the control-inductance plays an important role in the logic delay in circuits with a fan-out of /spl ges/3. The mutual coupling between device and control line results in a crosstalk, which has to be considered in the design by a certain noise margin. For high-performance circuits, Josephson devices with a low ratio of control-line inductance to device inductance are required; besides other advantages, the interferometer meets this requirement better than the in-line Josephson junction.