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IEEE Journal of Solid-State Circuits

Dynamic effects in Josephson devices operated as logic gates

Werner Bächtold

Published Oct 1, 1979• 2 citations
Publisher

Abstract

The dynamic behavior of Josephson devices, in particular interferometers, is investigated with simple approximations and computer simulations. It is shown that in the latching and in the nonlatching operation modes, the control-inductance plays an important role in the logic delay in circuits with a fan-out of /spl ges/3. The mutual coupling between device and control line results in a crosstalk, which has to be considered in the design by a certain noise margin. For high-performance circuits, Josephson devices with a low ratio of control-line inductance to device inductance are required; besides other advantages, the interferometer meets this requirement better than the in-line Josephson junction.

DOI
10.1109/jssc.1979.1051290

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IEEE Transactions on Applied Superconductivity•Jun 1, 1997•2 citations
The dynamic behavior of Josephson devices, in particular interferometers, is investigated with simple approximations and computer simulations. It is shown that in the latching and in the nonlatching operation modes, the control-inductance plays an important role in the logic delay in circuits with a fan-out of /spl ges/3. The mutual coupling between device and control line results in a crosstalk, which has to be considered in the design by a certain noise margin. For high-performance circuits, Josephson devices with a low ratio of control-line inductance to device inductance are required; besides other advantages, the interferometer meets this requirement better than the in-line Josephson junction.
This paper describes the design, fabrication and characterization of damped three-junction interferometers suitable for LSI latching logic. The high speed and low power dissipation of Josephson interferometers make them ideal devices for logic applications. However, their inherent high Q gives rise to resonances which appear as current steps in the quasiparticle curve. If not controlled, these current steps can interfere with the proper operation of logic circuits. Studies have shown that these resonances can be effectively damped by shunting the interferometer inductance with a small resistance. In this work the interferometers were made by placing the interferometer loops parallel to the groundplane and clustering the Josephson junctions together. This minimized the loop inductance associated with the counterelectrode which in turn meant that adequate damping could be achieved with metallurgically compatible short resistors connected only to the base electrode. The resultant structure with two overlying control lines each 2.5μm wide had an area of 0.008mm2. The Josephson junctions were 5μm in diameter. The measured damped resonance characteristics and threshold characteristics (Ig(Vg) and Im(Ic) respectively) of these structures agreed very well with theory.
We propose non-latching gates based on Superconducting QUantum Interference Device (SQUID) and logic circuits based on it. The gate consists of a 3-junction-SQUID coupled with an RF-SQUID inductively. According to numerical simulation, the wide bias margin reached /spl plusmn/52%. Adopting the magnetic coupling to apply input signals, the fan-out larger than unity was obtained without reducing signal current level. These consequences enabled us to realize complicated logic functions using this gate, The gate delay was 4.5ps at Jc=10kA/cm/sup 2/. An EXOR gate composed of two gates had the bias margin of /spl plusmn/35% and the delay time of 12ps. The operation in non-latching mode is also suitable for digital circuits based on HTS junctions.
It has generally been assumed that the switching dynamics of Josephson logic devices can be well approximated by treating the Josephson device as a capacitatively-shunted switch which opens instantaneously when a control current crosses threshold. In this approximation, the switching delay is proportional to RC, where R = load resistance and C = device capacitance. However, we show here that the above approximation is quite incorrect in the technologically important case of logic interferometers in which resonances are suppressed by internal damping. We treat in detail the case of damped two-junction interferometers with step-function control current. Analysis of the equations of motion shows that in addition to the RC delay there is an initial turn-on delay during which the output voltage is very small, and which is most pronounced for heavy internal damping. It consists of the time required for the difference in phase between the two junctions to increase to a critical value, followed by approximately the first half-cycle of growth of the average of the junction phases. The turn-on delay is a strong function of overdrive, (i.e., the factor by which the control current amplitude exceeds threshold), being smallest at large overdrives, and scales as (C/i0)1/2, where i0= junction critical current. Hence it can be reduced by miniaturization and/or increased junction current density. For parameter values typical of 5μm Josephson circuit technology, the turn-on delay is on the order of 10pS at large overdrives (≃2).
A 1:2:1 Josephson interferometer has been fabricated with small-area, high–current-density tunnel junctions. The short intrinsic RC times of these junctions result in device I-V characteristics with reduced hysteresis suitable for use in nonlatching logic circuits. The control current for this interferometer was fed directly, and asymmetrically, into the base electrode. Critical current versus control current measurements indicate that this device has a current gain greater than unity. The interferometer described represents an exploratory study of circuit design incorporating low-hysteresis junctions.
Josephson latching logic gates require an ac power supply for correct operation. Owing to the difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer-based logic gates. Experimental evaluation of the multi-gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results are discussed.