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Applied Physics Letters

Quantum interference Josephson logic devices

H. H. Zappe

Published Oct 15, 1975• 50 citations
Publisher

Abstract

Experiments with latching and nonlatching quantum interference logic devices are described. The device is a three-junction interferometer, switching with control currents of <0.5 mA. Simple logic functions have been performed with dc-powered nonlatching devices having a power dissipation of <40 nW in continuous operation.
DOI
10.1063/1.88520

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This paper describes the design, fabrication and characterization of damped three-junction interferometers suitable for LSI latching logic. The high speed and low power dissipation of Josephson interferometers make them ideal devices for logic applications. However, their inherent high Q gives rise to resonances which appear as current steps in the quasiparticle curve. If not controlled, these current steps can interfere with the proper operation of logic circuits. Studies have shown that these resonances can be effectively damped by shunting the interferometer inductance with a small resistance. In this work the interferometers were made by placing the interferometer loops parallel to the groundplane and clustering the Josephson junctions together. This minimized the loop inductance associated with the counterelectrode which in turn meant that adequate damping could be achieved with metallurgically compatible short resistors connected only to the base electrode. The resultant structure with two overlying control lines each 2.5μm wide had an area of 0.008mm2. The Josephson junctions were 5μm in diameter. The measured damped resonance characteristics and threshold characteristics (Ig(Vg) and Im(Ic) respectively) of these structures agreed very well with theory.
A new dc-powered Josephson latch has been designed and experimentally investigated.A latch is defined as a digital circuit in which information can be stored in a controlled manner. The latch we describe here consists of a nonlatching interferometer in series with a superconducting storage loop containing a second interferometer. Within the nominal operating region the latch has only two stable states and it does not display the problem of falling into a stable faulty state, in which the latch would respond to neither of its inputs (SET or RESET). Computer simulations using nominal 2.5-μm technology-device models indicate that the latch changes state in about 80 ps.
The dynamic behavior of Josephson devices, in particular interferometers, is investigated with simple approximations and computer simulations. It is shown that in the latching and in the nonlatching operation modes, the control-inductance plays an important role in the logic delay in circuits with a fan-out of /spl ges/3. The mutual coupling between device and control line results in a crosstalk, which has to be considered in the design by a certain noise margin. For high-performance circuits, Josephson devices with a low ratio of control-line inductance to device inductance are required; besides other advantages, the interferometer meets this requirement better than the in-line Josephson junction.
A 1:2:1 Josephson interferometer has been fabricated with small-area, high–current-density tunnel junctions. The short intrinsic RC times of these junctions result in device I-V characteristics with reduced hysteresis suitable for use in nonlatching logic circuits. The control current for this interferometer was fed directly, and asymmetrically, into the base electrode. Critical current versus control current measurements indicate that this device has a current gain greater than unity. The interferometer described represents an exploratory study of circuit design incorporating low-hysteresis junctions.
Thermal noise induced switching of Josephson logic devices is studied, both theoretically and experimentally. The results are critical for the design of the operating bias points for these devices. An analysis of the relevant energy contours shows that a three-junction superconducting quantum interference device has the same noise switching rate as a point junction with the same maximum critical current. Experimental results, for the dependence of the thermal noise induced switching rate on the gate current bias ratio, are in very good agreement with the theory.