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Journal of Applied Physics

Current-injection Josephson latch employing a single-flux quantum. I

J. Sone, Toshishige Yamada

Published May 1, 1986• 2 citations
Publisher

Abstract

A new current-injection Josephson latch employing a single-flux quantum is proposed. It has a master-slave circuit configuration and operates under ac power supply. In the circuit, data are stored as a circulating current in a superconducting loop consisting of a single junction and inductances. A two-junction interferometer gate directly coupled to the loop reads out the stored data. Dual-rail signals are generated from the read-out data by Josephson junctions and resister-coupled Josephson logic gates. The isolation between a master circuit and a slave circuit is realized using high-impedance states in the Josephson junctions. The circuit design and computer-simulation results on the circuit operation are described in this paper.

DOI
10.1063/1.336901

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A new current-injection Josephson latch employing a single-flux quantum is proposed. It has a master-slave circuit configuration and operates under ac power supply. In the circuit, data are stored as a circulating current in a superconducting loop consisting of a single junction and inductances. A two-junction interferometer gate directly coupled to the loop reads out the stored data. Dual-rail signals are generated from the read-out data by Josephson junctions and resister-coupled Josephson logic gates. The isolation between a master circuit and a slave circuit is realized using high-impedance states in the Josephson junctions. The circuit design and computer-simulation results on the circuit operation are described in this paper.
A new type of single flux quantum logic gate is proposed, which can perform unilateral propagation of signal without using three-phase clock. This gate is designed to be built with bridge-type Josephson junctions. A basic logic gate consists of two one-junction interferometers coupled by superconducting interconnecting lines, and the logical states are represented by zero or one quantized fluxoid in one of one-junction interferometers. The bias current of the unequal magnitude to each of the two one-junction interferometers results in unilateral signal flow. By adjusting design parameters such as the ratio of the critical current of Josephson junctions and the inductances, circuits with the noise immunity of greater than 50% with respect to the bias current have been designed. Three cascaded gates were modeled and simulated on a computer, and the unilateral signal flow was confirmed. The simulation also shows that a switching delay about 2 picoseconds is feasible.
A novel current-injection Josephson latch with a single-flux quantum memory is experimentally verified. The experimental latch is fabricated by 5-μm Pb-alloy technology and occupies an area of 270×175 μm2, achieving one order of magnitude area reduction compared to magnetically coupled latch. In low-frequency experiments, the proper operation of a single latch under arbitrary input conditions and the proper data transfer from latch to latch are observed. In high-speed experiments, the proper operation of a single latch with cycle time down to 3.7 ns is observed, which is limited by the high-speed restriction of the test instruments at room temperature. These results show the possibility that the complete current injection logic system can be constructed by combining the present latch and current-injection logic gates.
A Josephson SFQ (single flux quantum) shift register circuit operating under a two-phase power was designed and tested. The test cell was fabricated using the Nb/AlO/sub x//Nb junction SNEAP process. The main data latch is DC biased; the data storage is accomplished by the transfer of a single flux quantum in or out of a SQUID (superconducting quantum interference device) superconducting loop. A two-phase sinusoidal clock with offset is used to operate the circuit. Simulations verify that the operating frequency can go beyond 70 GHz, with operating margins exceeding 20%. Preliminary measurements indicate that the circuit operates as intended.>
A new dc-powered Josephson latch has been designed and experimentally investigated.A latch is defined as a digital circuit in which information can be stored in a controlled manner. The latch we describe here consists of a nonlatching interferometer in series with a superconducting storage loop containing a second interferometer. Within the nominal operating region the latch has only two stable states and it does not display the problem of falling into a stable faulty state, in which the latch would respond to neither of its inputs (SET or RESET). Computer simulations using nominal 2.5-μm technology-device models indicate that the latch changes state in about 80 ps.
A Josephson superconducting quantum interference device (SQUID) digital logic family was developed that uses the R/sub nn/ region of a Josephson junction (JJ) to compensate for variations in where R/sub nn/ is the effective resistance of a JJ in the linear I-V region beyond the gap. The basic compensating junction logic (CJL) circuit is two 2-input-OR 1-2-1 interferometer isolators that, when switched, inject current into a 2-input-AND 1-2-1 interferometer. The R/sub nn/ region of several JJs is used in series with a resistor to set the current from the power supply to the 2-input-OR interferometers. The 2-input-AND interferometer is implemented with both current injection and magnetic coupling. The latch circuit uses both current injection and magnetic coupling design techniques to increase the range of I/sub O/, inductance, and resistance variation over which the latch will function correctly. Experimental measurements of CJL circuits are described.>
A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.