Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Journal of Solid-State Circuits

Sub-100 ps experimental Josephson interferometer logic gates

M. Klein, Dennis Herrell

Published Oct 1, 1978• 44 citations
Publisher

Abstract

Josephson interferometer logic gates have been operated experimentally with an average logic delay of 55 ps per stage. The gates operated with an AC power supply in a latching mode with a reset capability consistent with a machine cycle time less than 5 ns. OR, AND, and INVERT functions and fanout capability were demonstrated. Dissipation per gate was about 2.0 /spl mu/W.

DOI
10.1109/jssc.1978.1051103

Related papers

Delay measurement of experimental 2.5-μm Josephson current injection logic (CIL)

Tushar R. Gheewala

Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10−16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.

Applied Physics Letters•May 15, 1979•11 citations

Logic delays of 5-μm current-switched Josephson gates

S. S. Pei

Logic delays of a current-switched latching gate called the Josephson atto-Weber switch and its use in a dc powered flip-flop module have been investigated. Experimental circuits with cascade chains of 31 gates were fabricated using 5-μm square lead alloy tunnel junctions. Delays were measured on both the latching and the unlatching chains. The experimental circuits demonstrate operation faster than those reported for other Josephson gate designs using the same linewidth. For the latching OR gate with fanout of 3, the shortest measured gate delay is 15 ps.

Applied Physics Letters•Apr 15, 1982•11 citations

Multi-gigahertz operation of 3-junction-interferometer-based Josephson latching logic circuits

W. Hioe, M. Hosoya, S. Kominami +2 more

Josephson latching logic gates require an ac power supply for correct operation. Owing to the difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer-based logic gates. Experimental evaluation of the multi-gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results are discussed.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•2 citations

High-performance Josephson interferometer latching logic and power supplies

Dennis Herrell, P. Arnett, M. Klein

This paper reviews some recent measuremtns on high‐performance Josephson latching logic, and discusses a compatible ac power scheme which provides good voltage regulation and low clock skew performance for a large computing machine.

AIP conference proceedings•Jan 1, 1978•12 citations

Dynamic effects in Josephson devices operated as logic gates

Werner Bächtold

The dynamic behavior of Josephson devices, in particular interferometers, is investigated with simple approximations and computer simulations. It is shown that in the latching and in the nonlatching operation modes, the control-inductance plays an important role in the logic delay in circuits with a fan-out of /spl ges/3. The mutual coupling between device and control line results in a crosstalk, which has to be considered in the design by a certain noise margin. For high-performance circuits, Josephson devices with a low ratio of control-line inductance to device inductance are required; besides other advantages, the interferometer meets this requirement better than the in-line Josephson junction.

IEEE Journal of Solid-State Circuits•Oct 1, 1979•2 citations

A Josephson dc-powered latch

Sang H. Dhong, Tushar R. Gheewala

A new dc-powered Josephson latch has been designed and experimentally investigated.A latch is defined as a digital circuit in which information can be stored in a controlled manner. The latch we describe here consists of a nonlatching interferometer in series with a superconducting storage loop containing a second interferometer. Within the nominal operating region the latch has only two stable states and it does not display the problem of falling into a stable faulty state, in which the latch would respond to neither of its inputs (SET or RESET). Computer simulations using nominal 2.5-μm technology-device models indicate that the latch changes state in about 80 ps.

Applied Physics Letters•Jun 1, 1981•6 citations
Josephson interferometer logic gates have been operated experimentally with an average logic delay of 55 ps per stage. The gates operated with an AC power supply in a latching mode with a reset capability consistent with a machine cycle time less than 5 ns. OR, AND, and INVERT functions and fanout capability were demonstrated. Dissipation per gate was about 2.0 /spl mu/W.
Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10−16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.
Logic delays of a current-switched latching gate called the Josephson atto-Weber switch and its use in a dc powered flip-flop module have been investigated. Experimental circuits with cascade chains of 31 gates were fabricated using 5-μm square lead alloy tunnel junctions. Delays were measured on both the latching and the unlatching chains. The experimental circuits demonstrate operation faster than those reported for other Josephson gate designs using the same linewidth. For the latching OR gate with fanout of 3, the shortest measured gate delay is 15 ps.
Josephson latching logic gates require an ac power supply for correct operation. Owing to the difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer-based logic gates. Experimental evaluation of the multi-gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results are discussed.
The dynamic behavior of Josephson devices, in particular interferometers, is investigated with simple approximations and computer simulations. It is shown that in the latching and in the nonlatching operation modes, the control-inductance plays an important role in the logic delay in circuits with a fan-out of /spl ges/3. The mutual coupling between device and control line results in a crosstalk, which has to be considered in the design by a certain noise margin. For high-performance circuits, Josephson devices with a low ratio of control-line inductance to device inductance are required; besides other advantages, the interferometer meets this requirement better than the in-line Josephson junction.
A new dc-powered Josephson latch has been designed and experimentally investigated.A latch is defined as a digital circuit in which information can be stored in a controlled manner. The latch we describe here consists of a nonlatching interferometer in series with a superconducting storage loop containing a second interferometer. Within the nominal operating region the latch has only two stable states and it does not display the problem of falling into a stable faulty state, in which the latch would respond to neither of its inputs (SET or RESET). Computer simulations using nominal 2.5-μm technology-device models indicate that the latch changes state in about 80 ps.