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AIP conference proceedings

High-performance Josephson interferometer latching logic and power supplies

Dennis Herrell, P. Arnett, M. Klein

Published Jan 1, 1978• 12 citations
Publisher

Abstract

This paper reviews some recent measuremtns on high‐performance Josephson latching logic, and discusses a compatible ac power scheme which provides good voltage regulation and low clock skew performance for a large computing machine.
DOI
10.1063/1.31381

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Josephson latching logic gates require an ac power supply for correct operation. Owing to the difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer-based logic gates. Experimental evaluation of the multi-gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results are discussed.
A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.
We have developed an ac power distribution scheme which provides switched regulated power of alternating polarity (no rectification necessary) for Josephson interferometer latching logic circuits. Distribution from the power source relies on a tree system of thin film transformers having single primaries and multiple secondaries to maintain low current levels and small phase skews throughout the system. Power signals are clipped on chip to the desired voltage supply level by series connected large area Josephson junctions ("regulator" junctions) and distributed across the chip by voltage busses. Supply resistors between the regulated voltage bus and the logic circuits define the operating current level. A detailed design is presented for a specific interferometer latching circuit family. We report experimental data on the two major components of the power system design - the regulators and the transformers. A series string of four regulator junctions provides a trapezoidal waveform of 11 mV amplitude at > 66% logic duty cycle (that portion of the machine cycle in which logic operations can be performed). Thin film transformers have their designed inductance (350 pH) and coupling coefficient ( > .90).
A new dc-powered Josephson latch has been designed and experimentally investigated.A latch is defined as a digital circuit in which information can be stored in a controlled manner. The latch we describe here consists of a nonlatching interferometer in series with a superconducting storage loop containing a second interferometer. Within the nominal operating region the latch has only two stable states and it does not display the problem of falling into a stable faulty state, in which the latch would respond to neither of its inputs (SET or RESET). Computer simulations using nominal 2.5-μm technology-device models indicate that the latch changes state in about 80 ps.