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IEEE Transactions on Electron Devices

Multi-input Josephson AND gate with ladder structure

Hideo Suzuki, K. Gotoh, T. Imamura, S. Hasuo

Published Mar 1, 1993• 0 citations
Publisher

Abstract

A multi-input AND gate composed of multiple stages, each with a three-junction interferometer and a single junction (ladder structure) is proposed. The number of inputs to this multi-input with multi-stage AND gate can easily be extended by systematically increasing the number of stages without decreasing the operating margin. The design and experimental results are described. Operating margins of the six-input AND gate were +or-30% (from simulation) and +or-20% (from experiment). The operating speed, simulated for 2.5- mu m-diameter junctions, was 60 ps, whereas the measured speed was 130 ps. The difference seems to be due to circuit parameter spread because the chip used for measuring the speed had large critical current deviation.>

DOI
10.1109/16.199374

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•Jan 1, 1997•0 citations
A multi-input AND gate composed of multiple stages, each with a three-junction interferometer and a single junction (ladder structure) is proposed. The number of inputs to this multi-input with multi-stage AND gate can easily be extended by systematically increasing the number of stages without decreasing the operating margin. The design and experimental results are described. Operating margins of the six-input AND gate were +or-30% (from simulation) and +or-20% (from experiment). The operating speed, simulated for 2.5- mu m-diameter junctions, was 60 ps, whereas the measured speed was 130 ps. The difference seems to be due to circuit parameter spread because the chip used for measuring the speed had large critical current deviation.>
The gate delay of a single CIL AND gate is measured with a Josephson sampler. The CIL gate consists of a CIL interferometer preceded by a three-junction SQUID isolation stage. The smallest delay observed was 6 ps. Simulation results and sampling measurements of a gate designed to switch to 3Vgare also reported. Processing variations precluded successful operation of the higher-voltage gate. The simulations suggest that this failure is due to the large difference of the average critical current from the design value. Scaling arguments show that for small-scale circuits high-speed operation with gate delays of a few picoseconds can be achieved with junction dimensions approximately equal to the Josephson penetration depth.
Josephson latching logic gates require an ac power supply for correct operation. Owing to the difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer-based logic gates. Experimental evaluation of the multi-gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results are discussed.
A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.
Measurements on large arrays of Josephson interferometers were carried out to obtain individual device parameters and their spread. Each array contained 784 identical interferometers with junction diameters of 5 and 7 μm and was deposited on a 6.35×6.35-mm Si chip. Threshold currents Im(0), subgap resistances Rj, and Vm —the product of Rj and Im(0) —were investigated. Statistical analysis indicated that the standard deviation σ of Im(0) and Rj ranged between 6 and 18% and that of Vm ranged between 5 and 7%. A systematic spatial dependence of Im(0) and Rj on the chips was obtained which is attributed as being due to nonuniformities in the rf oxygen discharge used to form the tunnel barrier. With improvements in the process, namely, eliminating these nonuniformities, the standard deviation in Im(0) (and Rj) can be reduced to about 5%. From the observed variations in the junction areas it is estimated that the random variation in the Josephson current density is about 4%. Large scale applications of these interferometers in the design of computer memory and logic thus seem feasible.
In order to develop superconducting Digital Signal Processors (DSP's), we have been studying a superconducting 1-bit Arithmetic Logic Unit (ALU). This ALU has the simplest function of AND, OR, ADD (addition), and SUB (subtraction). The ALU operates in a 3-stage pipeline. All logic functions such as AND, OR, and SUM (summation) can be executed within a single stage of the pipeline. In order to achieve the high-speed operation of the ALU, we proposed and designed a novel 3-input XOR gate, which can operate in only one logic stage. Our simulation study showed that all components of the ALU can operate up to 50 GHz. These ALU components were fabricated and tested at low speed. Large bias margins of more than /spl plusmn/37% were achieved. The designed ALU's were laid out and fabricated with an Nb process. The ALU occupied the area of 1200 /spl mu/m /spl times/ 2600 /spl mu/m, which contains 560 Josephson junctions (JJ's).
Josephson latching logic gates require an ac power supply for correct operation. Owing to difficulty in fabricating Josephson regulators for large power currents, multi-phase sinusoidal power supply is the preferred method for multi-gigahertz operation. However, the inherently variable ac power reduces device margin for covering process variations. As a result, there exists a strong relationship between circuit size, maximum operating frequency and circuit throughput for a given available margin. The trade-offs between these performance criteria are analyzed for 3-junction-interferometer- based logic gates. Experimental evaluation of the multi- gigahertz operation of small circuits showed that careful design of power supply networks that reduce power supply fluctuations will be needed to maximize performance. Simulation and experimental results will be discussed.