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Journal of Applied Physics

Measurements of device parameters on large arrays of Josephson interferometers

S. Basavaiah, J. H. Greiner, H. H. Zappe, Sherwin J. Singer

Published Mar 1, 1980• 13 citations
Publisher

Abstract

Measurements on large arrays of Josephson interferometers were carried out to obtain individual device parameters and their spread. Each array contained 784 identical interferometers with junction diameters of 5 and 7 μm and was deposited on a 6.35×6.35-mm Si chip. Threshold currents Im(0), subgap resistances Rj, and Vm —the product of Rj and Im(0) —were investigated. Statistical analysis indicated that the standard deviation σ of Im(0) and Rj ranged between 6 and 18% and that of Vm ranged between 5 and 7%. A systematic spatial dependence of Im(0) and Rj on the chips was obtained which is attributed as being due to nonuniformities in the rf oxygen discharge used to form the tunnel barrier. With improvements in the process, namely, eliminating these nonuniformities, the standard deviation in Im(0) (and Rj) can be reduced to about 5%. From the observed variations in the junction areas it is estimated that the random variation in the Josephson current density is about 4%. Large scale applications of these interferometers in the design of computer memory and logic thus seem feasible.

DOI
10.1063/1.327779

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Measurements on large arrays of Josephson interferometers were carried out to obtain individual device parameters and their spread. Each array contained 784 identical interferometers with junction diameters of 5 and 7 μm and was deposited on a 6.35×6.35-mm Si chip. Threshold currents Im(0), subgap resistances Rj, and Vm —the product of Rj and Im(0) —were investigated. Statistical analysis indicated that the standard deviation σ of Im(0) and Rj ranged between 6 and 18% and that of Vm ranged between 5 and 7%. A systematic spatial dependence of Im(0) and Rj on the chips was obtained which is attributed as being due to nonuniformities in the rf oxygen discharge used to form the tunnel barrier. With improvements in the process, namely, eliminating these nonuniformities, the standard deviation in Im(0) (and Rj) can be reduced to about 5%. From the observed variations in the junction areas it is estimated that the random variation in the Josephson current density is about 4%. Large scale applications of these interferometers in the design of computer memory and logic thus seem feasible.
Josephson-junction interferometers have previously been proposed as memory devices in which information is stored as a single flux quantum, (SFQ). To investigate the feasibility of making large arrays of SFQ cells suitable for the memory of a cryogenic computer, arrays containing 80 interferometers have been made and measured. The prime objective was to determine the distribution of the dc Josephson current i1 within the arays and to compare it with the design value required for successful operation of all cells in high density arrays. The results show that a substantial fraction of the arrays has standard deviations in i1 less than the maximum allowable, thus demonstrating for the first time that such a memory can be made with present technology. The fabrication, measurement technique and a detailed analysis of the current distributions on the arrays are presented.
NbN/MgO/NbN tunnel junction fabrication has been developed using statistical experimental design for insertion into a Josephson LSI (large-scale integration) fabrication technology. Junction deposition conditions have been studied and correlated with structural characterization and junction I-V measurements. Josephson junctions with sum gaps as large as 5.0 mV and junction quality factor of 47 mV have been produced. Current density uniformity, a critical parameter in circuit design, has also been investigated. I/sub c/(O) uniformity at 4.2 K of a 4000 junction array was within sigma =3.1% and was +or-10% across 1 in/sup 2/. The utility of this junction process has been demonstrated by insertion into a standard circuit fabrication process that has produced logic circuit operation above 10 K.>
Abstract Josephson superconducting qubits and parametric amplifiers are prominent examples of superconducting quantum circuits that have shown rapid progress in recent years. As such devices become more complex, the requirements for reproducibility of their electrical properties across a chip are being tightened. Critical current of the Josephson junction Ic is the essential electrical parameter in a chip. So, its variation is to be minimized. According to the Ambegaokar–Baratoff formula, critical current is related to normal-state resistance, which can be measured at room temperature. In this study, we focused on the dominant source of non-uniformity for the Josephson junction critical current–junction area variation. We optimized Josephson junction fabrication process and demonstrated resistance variation of 9.8–4.4% and 4.8–2.3% across 22 × 22 mm2 and 5 × 10 mm2 chip areas, respectively. For a wide range of junction areas from 0.008 to 0.12 μm2, we ensure a small linewidth standard deviation of 4 nm measured over 4500 junctions with linear dimensions from 80 to 680 nm. We found that the dominate source of junction area variation limiting Ic{\mathrm{I}}_{\mathrm{c}}Ic​ I c reproducibility is the imperfection of the evaporation system. The developed fabrication process was tested on superconducting highly coherent transmon qubits (T1 > 100 μs) and a nonlinear asymmetric inductive element parametric amplifier.
We report the electrical properties of all niobium nitride(NbN) Josephson tunnel junctions with magnesium oxide(MgO) films as barriers in the temperature range 4.2-15 K. NbN/MgO/NbN Josephson tunnel junctions have large gap voltages(Vg=4.8-5.4 mV), large products of the maximum critical currents and the normal tunneling resistances(IcRn=3.15-3.35 mV), and small subgap leakage currents(Vm=13-138 mV) at 4.2 K. The junction parameters decreased with increase in temperature, but reasonably large junction parameters(for example, Vg=4.9 mV, IcRn=2.67 mV, and Vm=22 mV) have been obtained even at 9 K. The magnetic penetration depth in NbN electrodes has been measured up to 15 K using two-junction interferometers which consist of NbN/MgO/NbN junctions, NbN ground planes, and NbN control lines.
We present a fabrication scheme and testing results for epitaxial sub-micrometer Josephson junctions. The junctions are made using a high-temperature (1170 K) "via process" yielding junctions as small as 0.8 mu m in diameter by use of optical lithography. Sapphire (Al2O3) tunnel-barriers are grown on an epitaxial Re/Ti multilayer base-electrode. We have fabricated devices with both Re and Al top electrodes. While room-temperature (295 K) resistance versus area data are favorable for both types of top electrodes, the low-temperature (50 mK) data show that junctions with the Al top electrode have a much higher subgap resistance. The microwave loss properties of the junctions have been measured by use of superconducting Josephson junction qubits. The results show that high subgap resistance correlates to improved qubit performance.
Quantum metrology based on Josephson junction array reproduces the most accurate desired voltage by far, therefore being introduced to provide voltage standards worldwide. In this work, we quantitatively analyzed the dependence of the first Shapiro step height of the junction array at 70 GHz on the parameter spread of 8,000 Josephson junctions with an average critical current (Ic) of 3.5 mA and an average normal state resistance (Rn) of 40 mΩ, using numerical simulations based on the resistively shunted junction (RSJ) model. The results indicate an upper limit spread of the Ic and Rn of the Josephson junctions. Specifically, to keep the maximum first Shapiro step above 0.9 mA, the Ic standard deviation, σ, should not exceed 25%, and for it to stay above 0.5 mA, the Rn deviation should not exceed 9%. This analysis specifically clarifies the required level of manufacturing process sophistication for superconducting devices to realize high-temperature superconducting (HTS) quantum-based voltage standards.